AN2785 datasheet(14/51 Pages) STMICROELECTRONICS

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Application examples

AN2785

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Doc ID 14785 Rev 1

6.1.2

BOOT (floating) supply pin

To supply the high-side floating section of the gate driver, the bootstrap capacitor must be

placed between the BOOT pin 14 and the OUT pin 12. For a detailed description of the

proper dimensioning of the bootstrap capacitor, refer to Chapter 5. The capacitor must be

placed as close as possible to the related IC pins. The bootstrap diode required for the

charge of the bootstrap capacitor is integrated inside the L6393 device.

6.1.3

Logic input pins

The logic input pins must be connected to the controller with the guidelines provided in

Chapter 2

. If the application environment is very noisy and the logic input voltage is low (for

example, 3.3 V), it can be useful to place some small RC network (not showed in Figure 8)

in series with the logic input lines, in order to avoid false input triggering due to external

noise.

6.1.4

Dead time pin

The resistance value on the DT pin must be selected as per the indications in Chapter 4 and

in Figure 5. It is recommended to connect a capacitor with a value of at least 100 nF

between the DT and GND pins, as close as possible to the IC and with short PCB tracks.

6.1.5

Comparator

The comparator is completely uncommitted and both the two input pins are externally

available. Attention must be paid to the output pin CPOUT, which is inverted with respect to

the comparator inputs due to the open-drain transistor connected to the output.

6.1.6

Gate driver outputs: gate lines

The gates of the power switches and the gate driver outputs can be connected directly, but

usually some gate resistors are placed in series on the gate lines in order to limit the gate

current during commutations. The final target is to control the dVOUT/dt of each half-bridge

output and then reduce the EMI. A more detailed explanation of the mechanisms behind the

dVOUT/dt control through the gate resistors is provided in Section 6.4. The following

calculations should be considered as approximated analyses of the gate charge

phenomenon, and therefore, in order to obtain the proper sizing of the gate resistor, it is

always strongly recommended to evaluate the resulting power bridge transitions through

bench analyses.

As shown in Figure 8, the gate line is split into two paths, one for the turn ON (with, in the

example, a gate resistor of 33

Ω) and the other one for the turn OFF, using a small signal

diode as path selector. Using this specific topology, the equivalent turn OFF resistance is in

a first approximation the parallel of the turn OFF and the turn ON resistances (neglecting the

diode drop). In the example, the turn OFF resistance is set to 0

Ω to provide the lowest

resistance path for the turn OFF of the IGBT. In fact, as explained in the two following

paragraphs, low impedance on the gate driver turn OFF helps to reduce the induced turn

ON phenomenon.

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