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AN2785 Datasheet(PDF) 48 Page - STMicroelectronics

Part # AN2785
Description  L6393 half bridge gate driver
PDF  51 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN2785 Datasheet(HTML) 48 Page - STMicroelectronics

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Layout suggestions
AN2785
48/51
Doc ID 14785 Rev 1
10
Layout suggestions
Typically, for power applications using high voltages and large load currents, the board
layout of all circuits related to the power stage is important. Board layout includes different
aspects, such as track dimensions (length and width), circuit areas, but also the proper
routing of the traces and the optimized reciprocal arrangement of the various system
elements and power sources in the PCB area.
There are several reasons for paying attention to the layout, which include all the EMI
issues, both induced and perceived by the application, over-voltage spikes due to parasitic
inductances along the PCB traces, proper connection of the sense blocks and the logic
inputs of the L6393 device.
Figure 37
provides some layout guidelines and suggestions for a full-bridge application.
Figure 37.
Layout suggestion for a H-bridge power system
As explained in Section 6.1.6, the gate driving PCB traces should be designed as short as
possible and the circuit area should be minimized to avoid sensitivity of such structures to
surrounding noise. Typically, a good power system layout keeps the power IGBTs (or
MOSFETs) of each half-bridge as close as possible to the related gate driver.
Figure 37
shows a set of parasitic inductances related to the different circuit tracks. The
various inductance groups may have undesired effects which should be limited as much as
possible. Moreover, note that Figure 37 emphasizes parasitic inductances located on the
lines usually managing high voltages and fast current transitions, which are very noisy.
HVG
H.V.
OUT
LVG
L6393
LP1
GND
GND
inputs
control signals
uC
MINIMIZE
TO LIMIT
THE BELOW
GROUND SPIKE
ON OUT PIN
POWER GROUND
SIGNAL GROUND
DRIVER GROUND
MINIMIZE TO LIMIT THE NOISE
ON THE INPUT LOGIC SIGNALS AND ON THE
ANALOG OPAMP OUTPUT
NOT CRITICAL
BULK
CAPACITOR
+
MINIMIZE
THE LENGHT OF
THESE PATHS
(IF USED)
CHOSE RSENSE
WITH LOW
PARASITIC
INDUCTANCE
TRACKS SWITCHING WITH HIGH VOLTAGE
TRANSITIONS SHOULD BE KEPT FAR FROM
THE LOGIC AND SENSING LINES
MINIMIZE
THIS AREA
LP2
LP3
LP4
LP5
phase 1
LP4
L6393
phase 2
LP3
LP2
LP1
LOAD



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