PIC16LC773-04SLASHSP datasheet(138/200 Pages) MICROCHIP

138 / 200 page

PIC16C77X

DS30275A-page 138

Advance Information

12.10.1 INT INTERRUPT

External interrupt on RB0/INT pin is edge triggered:

either rising if bit INTEDG (OPTION_REG<6>) is set,

or falling, if the INTEDG bit is clear. When a valid edge

appears

the

RB0/INT

pin,

flag

bit

INTF

(INTCON<1>) is set. This interrupt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be cleared in software in the interrupt service rou-

tine before re-enabling this interrupt. The INT interrupt

can wake-up the processor from SLEEP, if bit INTE was

set prior to going into SLEEP. The status of global inter-

rupt enable bit GIE decides whether or not the proces-

sor branches to the interrupt vector following wake-up.

See Section 12.13 for details on SLEEP mode.

12.10.2 TMR0 INTERRUPT

An overflow (FFh

→ 00h) in the TMR0 register will set

flag bit T0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit T0IE

(INTCON<5>). (Section 4.0)

12.10.3 PORTB INTCON CHANGE

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit RBIE (INTCON<4>).

(Section 3.2)

12.11

Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key reg-

isters during an interrupt, i.e., W register and STATUS

Example 12-1 stores and restores the W and STATUS

registers. The register, W_TEMP, must be defined in

each bank and must be defined at the same offset from

the bank base address (i.e., if W_TEMP is defined at

0x20 in bank 0, it must also be defined at 0xA0 in bank

1).

The example:

Stores the W register.

Stores the STATUS register in bank 0.

Stores the PCLATH register.

Executes the interrupt service routine code

(User-generated).

Restores the STATUS register (and bank select

bit).

Restores the W and PCLATH registers.

EXAMPLE 12-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM

MOVWF

W_TEMP

;Copy W to TEMP register, could be bank one or zero

SWAPF

STATUS,W

;Swap status to be saved into W

CLRF

STATUS

;bank 0, regardless of current bank, Clears IRP,RP1,RP0

MOVWF

STATUS_TEMP

;Save status to bank zero STATUS_TEMP register

MOVF

PCLATH, W

;Only required if using pages 1, 2 and/or 3

MOVWF

PCLATH_TEMP

;Save PCLATH into W

CLRF

PCLATH

;Page zero, regardless of current page

BCF

STATUS, IRP

;Return to Bank 0

MOVF

FSR, W

;Copy FSR to W

MOVWF

FSR_TEMP

;Copy FSR from W to FSR_TEMP

:(ISR)

MOVF

PCLATH_TEMP, W

;Restore PCLATH

MOVWF

PCLATH

;Move W into PCLATH

SWAPF

STATUS_TEMP,W

;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF

STATUS

;Move W into STATUS register

SWAPF

W_TEMP,F

;Swap W_TEMP

SWAPF

W_TEMP,W

;Swap W_TEMP into W

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