MSP430F5259IRGCT datasheet(20/112 Pages) TI1

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MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903B – MAY 2013 – REVISED NOVEMBER 2015

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5.7

Schmitt-Trigger Inputs – General-Purpose I/O DVCC Domain

(1)

(P5.0 to P5.5, P6.0 to P6.7, PJ.0 to PJ.3, RSTDVCC)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

1.8 V

0.80

1.40

VIT+

Positive-going input threshold voltage

3 V

1.50

2.10

1.8 V

0.45

1.00

VIT–

Negative-going input threshold voltage

3 V

0.75

1.65

1.8 V

0.3

0.8

Vhys

Input voltage hysteresis (VIT+ – VIT–)

3 V

0.4

1.0

For pullup: VIN = VSS,

RPull

Pullup or pulldown resistor

Ω

For pulldown: VIN = VCC

Input capacitance

VIN = VSS or VCC

(1)

These same parametrics apply to the clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).

5.8

Schmitt-Trigger Inputs – General-Purpose I/O DVIO Domain

(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.4, P4.0 to P4.7, P7.0 to P7.5, RST/NMI, BSLEN)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VIO

MIN

TYP

MAX

UNIT

1.62 V

0.8

1.25

VIT+

Positive-going input threshold voltage

VCC = 3.0 V

1.98 V

1.1

1.40

1.62 V

0.3

0.7

VIT–

Negative-going input threshold voltage

VCC = 3.0 V

1.98 V

0.5

1.0

Vhys

Input voltage hysteresis (VIT+ – VIT–)

VCC = 3.0 V

1.62 V to 1.98 V

0.3

0.8

For pullup: VIN = VSS,

RPull

Pullup or pulldown resistor(1)

Ω

For pulldown: VIN = VIO

Input capacitance

VIN = VSS or VIO

(1)

Also applies to the RST pin when the pullup or pulldown resistor is enabled.

5.9

Inputs – Interrupts DVCC Domain Port P6

(P6.0 to P6.7)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

t(int)

External interrupt timing(1)

External trigger pulse duration to set interrupt flag

1.8 V, 3 V

(1)

An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals

shorter than t(int).

5.10 Inputs – Interrupts DVIO Domain Ports P1 and P2

(P1.0 to P1.7, P2.0 to P2.7)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VIO

(1)

MIN

MAX

UNIT

External trigger pulse duration to set interrupt flag,

1.62 V to

t(int)

External interrupt timing(2)

VCC = 1.8 V or 3.0 V

1.98 V

(1)

In all test conditions, VIO ≤ VCC.

(2)

An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals

shorter than t(int).

Specifications

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MSP430F5259IRGCT Datasheet(PDF) 20 Page - Texas Instruments

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