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MSP430F5259IRGCT Datasheet(PDF) 12 Page - Texas Instruments |
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MSP430F5259IRGCT Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 112 page ![]() MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256 MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252 SLAS903B – MAY 2013 – REVISED NOVEMBER 2015 www.ti.com Table 4-1. Terminal Functions (continued) TERMINAL NO.(2) I/O(1) SUPPLY DESCRIPTION NAME RGC ZQE General-purpose digital I/O with reconfigurable port mapping secondary function Default mapping: Clock signal input – USCI_B1 SPI slave P4.3/PM_UCB1CLK/ mode 44 D8 I/O DVIO PM_UCA1STE(5) Default mapping: Clock signal output – USCI_B1 SPI master mode Default mapping: Slave transmit enable – USCI_A1 SPI mode General-purpose digital I/O with reconfigurable port mapping secondary function P4.4/PM_UCA1TXD/ 45 D7 I/O DVIO PM_UCA1SIMO(5) Default mapping: Transmit data – USCI_A1 UART mode Default mapping: Slave in, master out – USCI_A1 SPI mode General-purpose digital I/O with reconfigurable port mapping secondary function P4.5/PM_UCA1RXD/ 46 C9 I/O DVIO PM_UCA1SOMI(5) Default mapping: Receive data – USCI_A1 UART mode Default mapping: Slave out, master in – USCI_A1 SPI mode General-purpose digital I/O with reconfigurable port mapping secondary function P4.6/PM_UCA3TXD/ 47 C8 I/O DVIO PM_UCA3SIMO(5) Default mapping: Transmit data – USCI_A3 UART mode Default mapping: Slave in, master out – USCI_A3 SPI mode General-purpose digital I/O with reconfigurable port mapping secondary function P4.7/PM_UCA3RXD/ 48 C7 I/O DVIO PM_UCA3SOMI(5) Default mapping: Receive data – USCI_A3 UART mode Default mapping: Slave out, master in – USCI_A3 SPI mode General-purpose digital I/O P7.0/UCA2TXD/UCA2SIMO (5) 49 B8, B9 I/O DVIO Transmit data – USCI_A2 UART mode Slave in, master out – USCI_A2 SPI mode General-purpose digital I/O P7.1/UCA2RXD/UCA2SOMI (5) 50 A9 I/O DVIO Receive data – USCI_A2 UART mode Slave out, master in – USCI_A2 SPI mode General-purpose digital I/O Clock signal input – USCI_B2 SPI slave mode P7.2/UCB2CLK/UCA2STE(5) 51 B7 I/O DVIO Clock signal output – USCI_B2 SPI master mode Slave transmit enable – USCI_A2 SPI mode General-purpose digital I/O P7.3/UCB2SIMO/UCB2SDA(5) 52 A8 I/O DVIO Slave in, master out – USCI_B2 SPI mode I2C data – USCI_B2 I2C mode General-purpose digital I/O P7.4/UCB2SOMI/UCB2SCL(5) 53 A7 I/O DVIO Slave out, master in – USCI_B2 SPI mode I2C clock – USCI_B2 I2C mode General-purpose digital I/O Slave transmit enable – USCI_B2 SPI mode P7.5/UCB2STE/UCA2CLK(5) 54 A6 I/O DVIO Clock signal input – USCI_A2 SPI slave mode Clock signal output – USCI_A2 SPI master mode BSLEN(5) 55 B6 I DVIO BSL enable with internal pulldown 12 Terminal Configuration and Functions Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254 MSP430F5253 MSP430F5252 |
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