MSP430F5259IRGCT datasheet(44/112 Pages) TI1

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MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903B – MAY 2013 – REVISED NOVEMBER 2015

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5.47 Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TEST

PARAMETER

MIN

TYP

MAX

UNIT

CONDITIONS

DVCC(PGM/ERASE) Program and erase supply voltage

1.8

3.6

IPGM

Average supply current from DVCC during program

IERASE

Average supply current from DVCC during erase

Average supply current from DVCC during mass erase or bank

IMERASE, IBANK

erase

tCPT

Cumulative program time

See (1)

Program and erase endurance

104

105

cycles

tRetention

Data retention duration

TJ = 25°C

100

years

tWord

Word or byte program time

See (2)

µs

tBlock, 0

Block program time for first byte or word

See (2)

µs

Block program time for each additional byte or word, except for last

tBlock, 1–(N–1)

See (2)

µs

byte or word

tBlock, N

Block program time for last byte or word

See (2)

µs

Erase time for segment, mass erase, and bank erase when

tErase

See (2)

available

MCLK frequency in marginal read mode

fMCLK,MRG

MHz

(FCTL4.MRG0 = 1 or FCTL4.MRG1 = 1)

(1)

The cumulative program time must not be exceeded when writing to a 128-byte flash block. This parameter applies to all programming

methods: individual word or byte write mode and block write mode.

(2)

These values are hardwired into the state machine of the flash controller.

5.48 JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VCC

VIO

MIN

TYP

MAX

UNIT

fSBW

Spy-Bi-Wire input frequency

2.2 V, 3 V

1.62 V to 1.98 V

MHz

tSBW,Low

Spy-Bi-Wire low clock pulse duration

2.2 V, 3 V

1.62 V to 1.98 V

0.025

µs

Spy-Bi-Wire enable time (TEST high to acceptance of first

tSBW, En

1.62 V to 1.98 V

µs

clock edge)(1)

tSBW,Rst

Spy-Bi-Wire return to normal operation time

2.2 V, 3 V

1.62 V to 1.98 V

100

µs

2.2 V

1.62 V to 1.98 V

fTCK

TCK input frequency for 4-wire JTAG(2)

MHz

3 V

1.62 V to 1.98 V

Rinternal

Internal pulldown resistance on TEST

2.2 V, 3 V

1.62 V to 1.98 V

Ω

(1)

Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the

first SBWTCK clock edge.

(2)

fTCK may be restricted to meet the timing requirements of the module selected.

Specifications

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Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254

MSP430F5253 MSP430F5252

MSP430F5259IRGCT Datasheet(PDF) 44 Page - Texas Instruments

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