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MSP430F5259IRGCT Datasheet(PDF) 41 Page - Texas Instruments |
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MSP430F5259IRGCT Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 112 page ![]() MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256 MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252 www.ti.com SLAS903B – MAY 2013 – REVISED NOVEMBER 2015 5.43 10-Bit ADC, Linearity Parameters over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 1.4 V ≤ (VeREF+ – VeREF–) ≤ 1.6 V, CVeREF+ = 20 pF ±1.0 Integral EI 2.2 V, 3 V LSB linearity error 1.6 V < (VeREF+ – VeREF–) ≤ VAVCC, CVeREF+ = 20 pF ±1.0 Differential ED 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF 2.2 V, 3 V ±1.0 LSB linearity error 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF, EO Offset error 2.2 V, 3 V ±1.0 LSB Internal impedance of source RS < 100 Ω 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF, EG Gain error 2.2 V, 3 V ±1.0 LSB ADC10SREFx = 11b Total unadjusted 1.4 V ≤ (VeREF+ – VeREF–), CVeREF+ = 20 pF, ET 2.2 V, 3 V ±1.0 ±2.0 LSB error ADC10SREFx = 11b 5.44 REF, External Reference over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT Positive external reference VeREF+ VeREF+ > VeREF– (2) 1.4 AVCC V voltage input Negative external reference VeREF– VeREF+ > VeREF– (3) 0 1.2 V voltage input (VeREF+ – Differential external reference VeREF+ > VeREF– (4) 1.4 AVCC V VeREF–) voltage input 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC10CLK = 5 MHz, ADC10SHTx = 0x0001, 2.2 V, 3 V –26 26 µA Conversion rate 200 ksps IVeREF+, Static input current IVeREF– 1.4 V ≤ VeREF+ ≤ VAVCC , VeREF– = 0 V, fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000, 2.2 V, 3 V –1 1 µA Conversion rate 20 ksps CVREF+, Capacitance at VeREF+ or See (5) 10 µF CVREF- VeREF- terminal (1) The external reference is used during ADC conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. (2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. (3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. (4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. (5) Two decoupling capacitors, 10 µF and 100 nF, should be connected to VREF to decouple the dynamic current required for an external reference source if it is used for the ADC10_A. See also the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Copyright © 2013–2015, Texas Instruments Incorporated Specifications 41 Submit Documentation Feedback Product Folder Links: MSP430F5259 MSP430F5258 MSP430F5257 MSP430F5256 MSP430F5255 MSP430F5254 MSP430F5253 MSP430F5252 |
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