MSP430F5259IRGCT datasheet(85/112 Pages) TI1

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P5.3/XT2OUT

P5DIR.3

P5IN.3

Module X IN

Module X OUT

P5OUT.3

P5REN.3

Pad Logic

P5DS.3

0: Low drive

1: High drive

Bus

Keeper

To XT2

P5SEL.2

XT2BYPASS

P5SEL.3

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

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SLAS903B – MAY 2013 – REVISED NOVEMBER 2015

6.10.7 Port P5, P5.3, Input/Output With Schmitt Trigger

Table 6-54. Port P5 (P5.2, P5.3) Pin Functions

CONTROL BITS AND SIGNALS(1)

PIN NAME (P5.x)

FUNCTION

P5DIR.x

P5SEL.2

P5SEL.3

XT2BYPASS

P5.2/XT2IN

P5.2 (I/O)

I: 0; O: 1

XT2IN crystal mode(2)

XT2IN bypass mode(2)

P5.3/XT2OUT

P5.3 (I/O)

I: 0; O: 1

XT2OUT crystal mode(3)

P5.3 (I/O)(3)

(1)

X = Don't care

(2)

Setting P5SEL.2 causes the general-purpose I/O to be disabled. Pending the setting of XT2BYPASS, P5.2 is configured for crystal

mode or bypass mode.

(3)

Setting P5SEL.2 causes the general-purpose I/O to be disabled in crystal mode. When using bypass mode, P5.3 can be used as

general-purpose I/O.

Detailed Description

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MSP430F5259IRGCT Datasheet(PDF) 85 Page - Texas Instruments

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