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MB9B360R Datasheet(PDF) 72 Page - Cypress Semiconductor |
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MB9B360R Datasheet(HTML) 72 Page - Cypress Semiconductor |
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72 / 166 page ![]() Document Number: 002-04872 Rev.*A Page 72 of 166 MB9B360R Series Parameter Symbol Pin name Conditions Frequency * 4 (MHz) Value Unit Remarks Typ * 1 Max * 2 Power supply current ICC VCC Normal operation* 5 (PLL) 72MHz 46 98 mA *3 When all peripheral clocks are ON 60MHz 40 92 48MHz 33 85 36MHz 27 78 24MHz 19 70 12MHz 11 61 8MHz 8.5 58 4MHz 5.5 55 72MHz 33 85 mA *3 When all peripheral clocks are OFF 60MHz 29 81 48MHz 25 76 36MHz 20 71 24MHz 15 65 12MHz 9.2 59 8MHz 6.9 56 4MHz 4.6 54 *1: Ta=+25°C, VCC=3.3V *2: Tj=+125°C, VCC=5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00) Parameter Symbol Pin name Conditions Frequency * 4 Value Unit Remarks Typ * 1 Max * 2 Power supply current ICC VCC Normal operation* 5 (built-in high-speed CR) 4MHz 3.3 51 mA *3 When all peripheral clocks are ON 2.8 51 mA *3 When all peripheral clocks are OFF Normal operation* 5 (sub oscillation) 32kHz 0.64 48 mA *3 When all peripheral clocks are ON 0.56 48 mA *3 When all peripheral clocks are OFF Normal operation* 5 (built-in low-speed CR) 100kHz 0.64 48 mA *3 When all peripheral clocks are ON 0.58 48 mA *3 When all peripheral clocks are OFF *1: Ta=+25°C, VCC=3.3V *2: Tj=+125°C, VCC=5.5V *3: When all ports are fixed. *4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2 *5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 000) |
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