MB9B360R datasheet(80/166 Pages) CYPRESS

80 / 166 page

Document Number: 002-04872 Rev.*A

Page 80 of 166

MB9B360R Series

12.4 AC Characteristics

12.4.1

Main Clock Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter

Symbol

Pin name

Conditions

Value

Unit

Remarks

Min

Max

Input frequency

FCH

X0,

VCC ≥ 4.5V

MHz

When crystal

oscillator is

connected

VCC < 4.5V

VCC ≥ 4.5V

MHz

When using

external clock

VCC < 4.5V

Input clock

cycle

tCYLH

VCC ≥ 4.5V

20.83

250

When using

external clock

VCC < 4.5V

250

Input clock

pulse width

PWH/tCYLH,

PWL/tCYLH

When using

external clock

Input clock

rising time and

falling time

tCF,

tCR

When using

external clock

Internal

operating

clock*

frequency

FCC

160

MHz

Base clock

(HCLK/FCLK)

FCP0

MHz

APB0 bus

clock*

FCP1

160

MHz

APB1 bus

clock*

FCP2

MHz

APB2 bus

clock*

Internal

operating

clock*

1 cycle

time

CYCC

6.25

Base clock

(HCLK/FCLK)

CYCP0

12.5

APB0 bus

clock*

CYCP1

6.25

APB1 bus

clock*

CYCP2

12.5

APB2 bus

clock*

*1: For more information about each

internal operating clock, see “Chapter: Clock” in “FM4 Family Peripheral Manual”.

*2: For about each APB bus which each peripheral is connected to, see

“Block Diagram” in this datasheet.

MB9B360R Datasheet(PDF) 80 Page - Cypress Semiconductor

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