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MB9B360R Datasheet(PDF) 95 Page - Cypress Semiconductor |
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MB9B360R Datasheet(HTML) 95 Page - Cypress Semiconductor |
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95 / 166 page  Document Number: 002-04872 Rev.*A Page 95 of 166 MB9B360R Series SDRAM Mode (VCC = 2.7V to 3.6V, VSS = 0V) Parameter Symbol Pin name Value Unit Min Max Output frequency tCYCSD MSDCLK - 32 MHz Address delay time tAOSD MSDCLK, MAD[15:0] 2 12 ns MSDCLK ↑→Data output delay time tDOSD MSDCLK, MADATA[31:0] 2 12 ns MSDCLK ↑→Data output Hi-Z time tDOZSD MSDCLK, MADATA[31:0] 2 20 ns MDQM[1:0] delay time tWROSD MSDCLK, MDQM[1:0] 1 12 ns MCSX delay time tMCSSD MSDCLK, MCSX8 2 12 ns MRASX delay time tRASSD MSDCLK, MRASX 2 12 ns MCASX delay time tCASSD MSDCLK, MCASX 2 12 ns MSDWEX delay time tMWESD MSDCLK, MSDWEX 2 12 ns MSDCKE delay time tCKESD MSDCLK, MSDCKE 2 12 ns Data set up time tDSSD MSDCLK, MADATA[31:0] 23 - ns Data hold time tDHSD MSDCLK, MADATA[31:0] 0 - ns Note: When the external load capacitance CL = 30pF |
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