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MB9B360R Datasheet(PDF) 98 Page - Cypress Semiconductor

Part # MB9B360R
Description  32-Bit ARM짰 Cortex짰 - M4F FM4 Microcontroller
PDF  166 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB9B360R Datasheet(HTML) 98 Page - Cypress Semiconductor

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Document Number: 002-04872 Rev.*A
Page 98 of 166
MB9B360R Series
12.4.12 UART Timing
Synchronous serial (SPI = 0, SCINV = 0)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
VCC < 4.5V
VCC ≥ 4.5V
Unit
Min
Max
Min
Max
Serial clock
cycle time
tSCYC
SCKx
Internal shift
clock
operation
4tCYCP
-
4tCYCP
-
ns
SCK↓→SOT
delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN→SCK↑
setup time
tIVSHI
SCKx,
SINx
50
-
30
-
ns
SCK↑→SIN
hold time
tSHIXI
SCKx,
SINx
0
-
0
-
ns
Serial clock "L"
pulse width
tSLSH
SCKx
External shift
clock
operation
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock "H"
pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT
delay time
tSLOVE
SCKx,
SOTx
-
50
-
30
ns
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
10
-
10
-
ns
SCK↑→SIN
hold time
tSHIXE
SCKx,
SINx
20
-
20
-
ns
SCK falling
time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
• The above characteristics apply to CLK synchronous mode.
• tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connected to, see
“Block Diagram” in this datasheet.
• These characteristics only guarantee the same relocate port number.
For example, the combination of SCLKx_0 and SOTx_1 is not guaranteed.
• When the external load capacitance CL = 30pF.



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