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MB9B360R Datasheet(PDF) 88 Page - Cypress Semiconductor

Part # MB9B360R
Description  32-Bit ARM짰 Cortex짰 - M4F FM4 Microcontroller
PDF  166 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB9B360R Datasheet(HTML) 88 Page - Cypress Semiconductor

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Document Number: 002-04872 Rev.*A
Page 88 of 166
MB9B360R Series
Separate Bus Access Synchronous SRAM Mode
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Pin name
Conditions
Value
Unit
Min
Max
Address delay time tAV
MCLK,
MAD[24:0]
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
MCSX delay time
tCSL
MCLK,
MCSX[7:0]
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
tCSH
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
MOEX delay time
tREL
MCLK,
MOEX
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
tREH
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
Data set up
→MCLK↑ time
tDS
MCLK,
MADATA[15:0]
VCC ≥ 4.5V
19
-
ns
VCC < 4.5V
37
MCLK↑→
Data hold time
tDH
MCLK,
MADATA[15:0]
VCC ≥ 4.5V
0
-
ns
VCC < 4.5V
MWEX delay time
tWEL
MCLK,
MWEX
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
tWEH
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
MDQM[1:0]
delay time
tDQML
MCLK,
MDQM[1:0]
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
tDQMH
VCC ≥ 4.5V
1
9
ns
VCC < 4.5V
12
MCLK↑→
Data output time
tODS
MCLK,
MADATA[15:0]
VCC ≥ 4.5V
MCLK+1
MCLK+18
ns
VCC < 4.5V
MCLK+24
MCLK↑→
Data hold time
tOD
MCLK,
MADATA[15:0]
VCC ≥ 4.5V
1
18
ns
VCC < 4.5V
24
Note: When the external load capacitance CL = 30pF



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