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MB9B360R Datasheet(PDF) 116 Page - Cypress Semiconductor |
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MB9B360R Datasheet(HTML) 116 Page - Cypress Semiconductor |
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116 / 166 page  Document Number: 002-04872 Rev.*A Page 116 of 166 MB9B360R Series High-speed synchronous serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin name Conditions VCC < 4.5V VCC ≥ 4.5V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 14 - 12.5 - ns 12.5* SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 5 - 5 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: • The above characteristics apply to CLK synchronous mode. • tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet. • These characteristics only guarantee the following pins. • No chip select : SIN4_1, SOT4_1, SCK4_1 • Chip select : SIN6_1, SOT6_1, SCK6_1, SCS6_1 • When the external load capacitance CL = 30pF. (For *, when CL = 10pF) |
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