MB9B360R datasheet(122/166 Pages) CYPRESS

122 / 166 page

Document Number: 002-04872 Rev.*A

Page 122 of 166

MB9B360R Series

When using high-speed synchronous serial chip select (SPI = 1, SCINV = 0, MS=0, CSLVL=1)

(VCC = 2.7V to 5.5V, VSS = 0V)

Parameter

Symbol

Conditions

VCC < 4.5V

VCC ≥ 4.5V

Unit

Min

Max

Min

Max

SCS

↓→SCK↓setup time

tCSSI

Internal shift clock

operation

(*1)-20

(*1)+0

(*1)-20

(*1)+0

SCK

↑→SCS↑ hold time

tCSHI

(*2)+0

(*2)+20

(*2)+0

(*2)+20

SCS deselect time

tCSDI

(*3)-20

+5tCYCP

(*3)+20

+5tCYCP

(*3)-20

+5tCYCP

(*3)+20

+5tCYCP

SCS

↓→SCK↓setup time

tCSSE

External shift clock

operation

3tCYCP+15

SCK

↑→SCS↑ hold time

tCSHE

SCS deselect time

tCSDE

3tCYCP+15

SCS

↓→SOT delay time

tDSE

SCS

↑→SOT delay time

tDEE

(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]

(*2): CSHD bit value×serial chip select timing operating clock cycle [ns]

(*3): CSDS bit value×serial chip select timing operating clock cycle [ns]

Notes:

• tCYCP indicates the APB bus clock cycle time.

About the APB bus number which UART is connected to, see “Block Diagram” in this datasheet.

• About CSSU, CSHD, CSDS, serial chip select timing operating clock, see “FM4 Family Peripheral Manual”.

• When the external load capacitance CL = 30pF.

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