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DP83266 Datasheet(PDF) 101 Page - National Semiconductor (TI) |
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DP83266 Datasheet(HTML) 101 Page - National Semiconductor (TI) |
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101 / 152 page ![]() 70 Control Information (Continued) Limit Data Register (LDR) The Limit Data Register (LDR) is used to hold the 8 least-significant Limit RAM data bits transferred in an LMOP service function (The most-significant data bit is in the Limit Address Register) This register is not altered upon reset Access Rules Address Read Write 10Dh Always Always Register Bits D7 D6 D5 D4 D3 D2 D1 D0 LRD7 LRD6 LRD5 LRD4 LRD3 LRD2 LRD1 LRD0 Bit Symbol Description D7–D0 LRD7–0 Limit RAM Data Bit 7 – 0 This bit contains the least-significant data bit read or written from or to a Limit RAM Register in an LMOP service function Bit LDR7 is a ‘‘don’t care’’ when using small (1 kByte) queues 101 |
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