ML7204-003 datasheet(7/214 Pages) LAPIS

7 / 214 page

FEDL7204-003-02

ML7204-003

7/214

QFP64

Symbol

I/O

When

PDNB

= “0”

Description

GSX0

“Hi-z” AMP0 output (10 k

 driving)

GSX1

“Hi-z” AMP1 output (10 k

 driving)

AIN1N

AMP1 inverted input

AVREF

“L”

Analog signal ground (1.4 V)

VFRO0

“Hi-z” AMP2 output (10 k

 driving)

VFRO1

“Hi-z” AMP3 output (10 k

 driving)

AGND

—

Analog ground (0.0 V)

DGND2

—

Digital ground (0.0 V)

12.288 MHz crystal interface, 12.288 MHz clock input

“H”

12.288 MHz crystal interface

DVDD2

—

Digital power supply

VREGOUT

—

Internal regulator voltage output pin (approx. 2.5 V)

VBG

—

Internal regulator reference voltage output pin

* Explanation of symbols used in the PDNB = “0” column

The symbols denote the following pin conditions when PDNB = “0”:

“I”

: Input a High or Low level signal to the pin.

“0”

: Input a Low level signal to the pin

“H”

: A High level signal is output from the pin.

“L”

: A Low level signal is output from the pin.

“Hi-Z”

: The pin goes into a Hi-Z state.

ML7204-003 Datasheet(PDF) 7 Page - LAPIS Semiconductor Co., Ltd.

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