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ML7204-003 Datasheet(PDF) 73 Page - LAPIS Semiconductor Co., Ltd. |
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ML7204-003 Datasheet(HTML) 73 Page - LAPIS Semiconductor Co., Ltd. |
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73 / 214 page  FEDL7204-003-02 ML7204-003 73/214 Control Registers Tables 5 shows the maps of control registers. CR6-CR9 are used for DSP internal data memory access. The changeable operation mode is indicated below each register name. Table 5 Control Register Map (1 of 4) Address Contents Reg Name A7-A0 B7 B6 B5 B4 B3 B2 B1 B0 R/W SPDN AFEB _EN AFEA _EN # # # SYNC _SEL OPE _STAT CR0 00h /E I/ I/ — — — I/ I/ R/W XDMWR XDMRD # # XDMWR _2 # # # CR1 01h I/E I/E — — I/E — — — R/W TGEN0 _RXAB TGEN0 _RX TGEN0 _CNT5 TGEN0 _CNT4 TGEN0 _CNT3 TGEN0 _CNT2 TGEN0 _CNT1 TGEN0 _CNT0 CR2 02h I/E I/E I/E I/E I/E I/E I/E I/E R/W TGEN1 _RXAB TGEN1 _TX TGEN1 _CNT5 TGEN1 _CNT4 TGEN1 _CNT3 TGEN1 _CNT2 TGEN1 _CNT1 TGEN1 _CNT0 CR3 03h I/E I/E I/E I/E I/E I/E I/E I/E R/W # # # # # # # # CR4 04h — — — — — — — — / READY # # # # # RXFLAG _CH2 RXFLAG _CH1 CR5 05h — — — — — — I/E I/E R/W Internal data memory access (high-order address/high-order data) A15/D15 A14/D14 A13/D13 A12/D12 A11/D11 A10/D10 A9/D9 A8/D8 CR6 06h I/E /W Internal data memory access (low-order access/low-order data) A7/D7 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 CR7 07h I/E /W Internal data memory access (high-order data) D15 D14 D13 D12 D11 D10 D9 D8 CR8 08h I/E R/W Internal data memory access (low-order data) D7 D6 D5 D4 D3 D2 D1 D0 CR9 09h I/E R/W # # # # # VFRO1 _SEL VFRO0 _SEL # CR10 0Ah — — — — — I/E I/E — R/W PCM _SEL1 PCM _SEL0 # PCMI3 _EN PCMO2 _EN PCMI2 _EN PCMI1 _EN PCMO1 _EN CR11 0Bh I/ I/ — /E /E /E /E /E R/W |
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