ML7204-003 datasheet(71/214 Pages) LAPIS

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FEDL7204-003-02

ML7204-003

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B. Time slot assignment function

The PCM interface of this LSI is compatible with the serial transmission rate from 64 kHz to 2.048 MHz.

Therefore, by connecting multiple LSIs on the PCM interface, it is possible to logically achieve PCM data

multiplexing of up to 32 slots at G.711(

-law/A-law) setting and up to 16 slots at 16-bit linear setting.

This LSI can be set up to 3 input time slots independently by using the following registers:

PCM input time slot selection register 1 (PCM_ITS1[4:0])

PCM input time slot selection register 2 (PCM_ITS2[4:0])

PCM input time slot selection register 3 (PCM_ITS3[4:0])

Also, 2 output time slots can be set independently by using the following registers:

PCM output time slot selection register 1(PCM_OTS1[4:0])

PCM output time slot selection register 2(PCM_OTS2[4:0])

Note that the following rules are applied for the setting of time slots.

(Note)

The number of bits of one time slot changes automatically according to the setting of the PCM coding format

(PCM_SELL [1:0])as follows.

16-bit linear setting: 16 bits

G.711 (

-law/A-law) setting: 8 bits

Therefore, the maximum number of time slots that can be set will be as follows:

16-bit linear setting: n/2

G.711 (

-law/A-law) setting: n

[n = (BCLK frequency)

 64 kHz]

Setting a time slot number greater than the largest time slot number indicated above is inhibited.

C. Application example

By connecting multiple LSIs on the PCM interface, two-way communication or three-way communication is

enabled.

C-1. Two-way communication

Figure 42 shows an application example of two-way communication by transmitting/receiving PCM data

between two ML7204 devices connected on the PCM interface.

Figure 42 Example of Connection for Two-Way Communication via PCM I/F

SYNC

BCLK

PCMI

PCMO

A-TEL1

ML7204

SYNC

BCLK

PCMI

PCMO

A-TEL2

ML7204

CLKOUT

CLKSEL

+3.3V

Crystal unit

 Output time slot selection register 1 (PCM_OTS1[4:0])

ML7204 #1: 00000b (output time slot “1”)

ML7204 #2: 00001b (output time slot “2”)

 Input time slot selection register 1 (PCM_ITS1[4:0])

ML7204 #1: 00001b (input time slot “2”)

ML7204 #2: 00000b (input time slot “1”)

Two-way communication can be achieved between A-TEL1 and A-TEL2 by

setting both the PCM output time slot 1 enable control register (PCM01_EN)

and the PCM input time slot 1 enable control register (PCMI1_EN) to “1” while

setting the time slots as shown above.

ML7204-003 Datasheet(PDF) 71 Page - LAPIS Semiconductor Co., Ltd.

ML7204-003 Datasheet(HTML) 71 Page - LAPIS Semiconductor Co., Ltd.

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