CAM35C44 datasheet(24/50 Pages) SMSC

24 / 50 page

HALF DUPLEX, Bit 2

When the HALF DUPLEX bit D2 is “0” (default),

the 16C550A UART in the IrCC 2.0 is in full

duplex mode. Full duplex mode has no effect on

the IrCC 2.0 SCE.

When the HALF DUPLEX bit is “1”, the IrCC 2.0

is in half duplex mode.

Half duplex mode is

typically required for all infrared transactions.

In half duplex mode, the IR Half Duplex Time-

Out will apply to IrCC 2.0 transmit/receive

direction mode changes (see section CR07 - IR

Half Duplex Time-Out on page 26). The IR Half

Duplex Time-Out does not apply to full duplex

mode.

IR_MODE, Bits 3 - 5

The IR_MODE bits D3 - D5 select the active

IrCC 2.0 encoder/decoder. The default is COM

(TABLE 17).

The IR_MODE bits are equivalent to the three

low-order Block Control bits in the IrCC 2.0 SCE

Configuration Register A.

TABLE 17 - CAM35C44 INFRARED PROTOCOL OPTIONS

IR_MODE[2:0]

MODE

DESCRIPTION

COM

16C550A UART (Default)

IrDA SIR-A

Up to 115.2Kbps, Variable 3/16ths Pulse

ASK IR

500KHz Carrier, Amplitude Shift Keyed IR

IrDA SIR-B

Up to 115.2Kbps, Fixed 1.6

#s Pulse

IrDA HDLC

0.576Mbps and 1.152Mbps

IrDA 4PPM

4Mbps

CONSUMER

Consumer (TV Remote) IR

RAW

Direct IR Diode Control

CR03 - Infrared Control B

The Infrared Control B register CR03 configures

the infrared interface and COM port clock select.

CR03

can

only

accessed

the

configuration state and only after the CSR has

been initialized to 03H. The default value of this

Bits[7:5,3:1] in the Infrared Control B register are

RESERVED.

TABLE 18 - IR CONTROL B REGISTER

DEFAULT

CR03

R/W

RESERVED

MIDI

RESERVED

HPMODE

0x01

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