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CAM35C44 Datasheet(PDF) 27 Page - SMSC Corporation |
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CAM35C44 Datasheet(HTML) 27 Page - SMSC Corporation |
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27 / 50 page ![]() 27 CR08 - Power Control The Power Control register CR08 contains the power control enables to select the various CAM35C44 power states (TABLE 25) and also includes a bit to configure the system clock source. CR08 can only be accessed in the configuration state and only after the CSR has been initialized to 08H. The default value of this register after power up is 00H (TABLE 23). Bits[7:6] in the Power Control register are RESERVED. TABLE 23 - POWER CONTROL REGISTER D7 D6 D5 D4 D3 D2 D1 D0 Default CR08 R/W RES INT_ OSC AUTO_ PWR SCE_ ON PLL_ ON ACE_ON OSC_ON 0x00 OSC_ON, Bit 0 The OSC_ON bit D0 determines the power state for CAM35C44 clock generator, independent of the clock source (see section INT_OSC, Bit 5 on page 28). When OSC_ON is “0” (default), the clock generator is powered down. When OSC_ON is “1”, the clock generator is running. ACE_ON, Bit 1 The ACE_ON bit D1 along with the AUTO_PWR bit D4 determines the power state for IrCC 2.0 ACE UART. When ACE_ON is “0” (default), the UART is powered down, regardless of the state of AUTO_PWR; i.e., when ACE_ON is “0”, UART wake-up events are disabled (see section AUTO_PWR, Bit 4). When ACE_ON is “1”, the UART is active. PLL_ON, Bit 2 The PLL_ON bit D2 determines the power state for the PLL clock multiplier. The PLL is required for IrDA transfers above 115.2Kbps. When PLL_ON is “0” (default), the PLL is powered down. When PLL_ON is “1”, the PLL is running. SCE_ON, Bit 3 The SCE_ON bit D3 determines the power state for the IrCC 2.0 SCE. The SCE is required for IrDA transfers above 115.2Kbps and for all Consumer IR transactions. When SCE_ON is “0” (default), the SCE is powered down. When SCE_ON is “1”, the SCE is active. AUTO_PWR, Bit 4 The AUTO_PWR bit D4 along with the ACE_ON bit D1 selects the auto power down state of the ACE UART (TABLE 24). When AUTO_PWR is “0” (default), the ACE auto power down state is disabled and the ACE UART power state is controlled solely by the ACE_ON bit (see section ACE_ON, Bit 1 on page 27). Note: If the ACE auto power state is disabled the ring indicator (nRI) and the RXD power-on wake-up events are disabled. When AUTO_PWR is “1” and ACE_ON is “1”, the ACE auto power down state is enabled and the following power management events are possible. |
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