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LAN9115 Datasheet(PDF) 104 Page - Microchip Technology |
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LAN9115 Datasheet(HTML) 104 Page - Microchip Technology |
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104 / 114 page  LAN9115 DS00002269A-page 104 2005-2016 Microchip Technology Inc. 6.9 EEPROM Timing The following specifies the EEPROM timing requirements for the LAN9115. FIGURE 6-9: EEPROM TIMING TABLE 6-9: EEPROM TIMING VALUES Symbol Description MIN TYP MAX Units tCKCYC EECLK Cycle time 1110 1130 ns tCKH EECLK High time 550 570 ns tCKL EECLK Low time 550 570 ns tCSHCKH EECS high before rising edge of EECLK 1070 ns tCKLCSL EECLK falling edge to EECS low 30 ns tDVCKH EEDIO valid before rising edge of EECLK (OUTPUT) 550 ns tCKHDIS EEDIO disable after rising edge EECLK (OUTPUT) 550 ns tDSCKH EEDIO setup to rising edge of EECLK (INPUT) 90 ns tDHCKH EEDIO hold after rising edge of EECLK (INPUT) 0 ns tCKLDIS EECLK low to data disable (OUTPUT) 580 ns tCSHDV EEDIO valid after EECS high (VERIFY) 600 ns tDHCSL EEDIO hold after EECS low (VERIFY) 0 ns tCSL EECS low 1070 ns |
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