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MSP432P411VIPZR Datasheet(PDF) 121 Page - Texas Instruments |
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MSP432P411VIPZR Datasheet(HTML) 121 Page - Texas Instruments |
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121 / 212 page  121 MSP432P4111, MSP432P4011, MSP432P411Y MSP432P401Y, MSP432P411V, MSP432P401V www.ti.com SLASEA0A – DECEMBER 2017 – REVISED FEBRUARY 2018 Submit Documentation Feedback Product Folder Links: MSP432P4111 MSP432P4011 MSP432P411Y MSP432P401Y MSP432P411V MSP432P401V Detailed Description Copyright © 2017–2018, Texas Instruments Incorporated Table 6-34. RSTCTL Registers (continued) REGISTER NAME ACRONYM OFFSET Reboot Reset Status RSTCTL_REBOOTRESET_STAT 118h Reboot Reset Status Clear RSTCTL_REBOOTRESET_CLR 11Ch CS Reset Status RSTCTL_CSRESET_STAT 120h CS Reset Status Clear RSTCTL_CSRESET_CLR 124h Table 6-35. SYSCTL_A Registers REGISTER NAME ACRONYM OFFSET Reboot Control SYS_REBOOT_CTL 0000h NMI Control and Status SYS_NMI_CTLSTAT 0004h Watchdog Reset Control SYS_WDTRESET_CTL 0008h Peripheral Halt Control SYS_PERIHALT_CTL 000Ch SRAM Size SYS_SRAM_SIZE 0010h SRAM Number of Banks SYS_SRAM_NUMBANKS 0014h SRAM Number of Blocks SYS_SRAM_NUMBLOCKS 0018h Flash Main Memory Size SYS_MAINFLASH_SIZE 0020h Flash Information Memory Size SYS_INFOFLASH_SIZE 0024h Digital I/O Glitch Filter Control SYS_DIO_GLTFLT_CTL 0030h IP Protected Secure Zone Data Access Unlock SYS_SECDATA_UNLOCK 0040h SRAM Bank Enable Control 0 SYS_SRAM_BANKEN_CTL0 0050h SRAM Block Retention Control 0 SYS_SRAM_BLKRET_CTL0 0070h SRAM Status SYS_SRAM_STAT 0090h Master Unlock SYS_MASTER_UNLOCK 1000h Boot Override Request 0 SYS_BOOTOVER_REQ0 1004h Boot Override Request 1 SYS_BOOTOVER_REQ1 1008h Boot Override Acknowledge SYS_BOOTOVER_ACK 100Ch Reset Request SYS_RESET_REQ 1010h Reset Status and Override SYS_RESET_STATOVER 1014h System Status SYS_SYSTEM_STAT 1020h 6.4 Memories on MSP432P4x1x MSP432P4x1x devices include flash memory and SRAM for general-application purposes. In addition, the devices include a backup memory (a portion of total available SRAM) that is retained in low-power modes. 6.4.1 Flash Memory MSP432P4x1x devices include a high-endurance low-power flash memory that supports up to a minimum of 20000 write or erase cycles. The flash memory is 128 bits wide, thereby enabling high code execution performance by virtue of each fetch returning up to four 32-bit instructions (or up to eight 16-bit instructions). The flash is further divided into two types of subregions: Main Memory and Information Memory. From a physical perspective the flash memory comprises of two banks, with the main and information memory regions divided equally between the two banks. This permits an application to carry out a simultaneous read or execute operation from one bank while the other bank may be undergoing a program or erase operation. The memory map of flash on MSP432P4x1x devices is shown in Figure 6-5. |
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