BLUENRG-2 datasheet(127/190 Pages) STMICROELECTRONICS

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BlueNRG-2

Functional details

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The TnA and TnB inputs can be configured to perform a counter pReset to 0xFFFF upon

reception of a valid capture event using TnAEN and TnBEN bits in TnMCTRL register. In

this case, the current value of the counter is transferred to the corresponding capture

software to determine the on-time, off-time, or period of an external signal, while reducing

CPU overhead.

In Figure 18: "MFT mode 2 block diagram" below the block diagram related to the MFT

mode 2.

Figure 18: MFT mode 2 block diagram

The input signal on TnA and TnB must have a pulse width equal to or greater than one

system clock cycle. The values captured in the TnCRB register at different times reflect the

elapsed time between transitions on the TnA pin. The same is true for the TnCRB register

and TnB pin. Each input pin can be configured to sense either positive-going or negative-

going transitions.

The timer can be configured to generate interrupts on reception of a transition on either

TnA or TnB, which can be enabled or disabled separately by the TnAIEN and TnBIEN bits.

An underflow of TnCNT1 can generate an interrupt if enabled by the TnCIEN bit.

Timer/Counter 2 can be used as a simple system timer in this mode of operation. TnCNT2

counts down with the clock selected by the Timer/Counter 2 clock selector, and can be

configured to generate an interrupt upon underflow if enabled by the TnDIEN bit.

TnCNT1 cannot operate in the pulse-accumulate or extemal-event counter modes, since

the TnB input is used as a capture input. Selecting either of these modes for TnCNT1

causes TnCNT1 to be stopped. However, all available clock source modes may be

BLUENRG-2 Datasheet(PDF) 127 Page - STMicroelectronics