CS5530A datasheet(123/259 Pages) NSC

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Functional Description (Continued)

3.7.2

VSA Technology Support Hardware

The CS5530A I/O companion incorporates the required

hardware in order to support the Virtual System Architec-

ture (VSA) technology for capture and playback of audio

using an external codec. This eliminates much of the hard-

ware traditionally associated with industry standard audio

functions.

XpressAUDIO software provides 16-bit compatible sound.

This software is available to OEMs for incorporation into

the system BIOS ROM.

3.7.2.1

VSA Technology

VSA technology provides a framework to enable software

implementation of traditionally hardware-only components.

VSA technology software executes in System Management

Mode (SMM), enabling it to execute transparently to the

operating system, drivers, and applications.

The VSA technology design is based upon a simple model

for replacing hardware components with software. Hard-

ware to be virtualized is merely replaced with simple

access detection circuitry which asserts the SMI# (System

Management Interrupt) pin when hardware accesses are

detected. The current execution stream is immediately pre-

empted, and the processor enters SMM. The SMM system

software then saves the processor state, initializes the VSA

technology execution environment, decodes the SMI

source and dispatches handler routines which have regis-

tered requests to service the decoded SMI source. Once

all handler routines have completed, the processor state is

restored and normal execution resumes. In this manner,

hardware accesses are transparently replaced with the

execution of SMM handler software.

Historically, SMM software was used primarily for the single

purpose of facilitating active power management for note-

book designs. That software’s only function was to manage

the power up and down of devices to save power. With high

performance processors now available, it is feasible to

implement, primarily in SMM software, PC capabilities tra-

ditionally provided by hardware. In contrast to power man-

agement code, this virtualization software generally has

strict performance requirements to prevent application per-

formance from being significantly impacted.

3.7.2.2

Audio SMI Related Registers

The SMI related registers consist of:

• Second Level Audio SMI Status Registers

• I/O Trap SMI and Fast Write Status Register

• I/O Trap SMI Enable Register

The Top SMI Status Mirror and Status Registers are the top

level of hierarchy for the SMI handler in determining the

source

SMI.

These

two

registers

are

F1BAR+Memory

Offset

00h

(Status

Mirror)

and

F1BAR+Memory Offset 02h (Status). The registers are

identical except that reading the register at F1BAR+Mem-

ory Offset 02h clears the status.

Second Level Audio SMI Status Registers

The second level of audio SMI status reporting is set up

very much like the top level. There are two status reporting

registers, one “read only” (mirror) and one “read to clear”.

The data returned by reading either offset is the same (i.e.,

SMI was caused by an audio related event). The difference

between F3BAR+Memory Offset 12h and 10h (mirror) is in

the ability to clear the SMI source at 10h.

Figure 3-22 shows an SMI tree for checking and clearing

thesourceofanaudio SMI. Only theaudio SMIbit is

detailed here. For details regarding the remaining bits in

the Top SMI Status Mirror and Status Registers refer to

Table 4-17 "F1BAR+Memory Offset xxh: SMI Status and

ACPI Timer Registers" on page 183.

I/O Trap SMI and Fast Write Status Register

This 32-bit read-only register (F3BAR+Memory Offset 14h)

not only indicates if the enabled I/O trap generated an SMI,

but also contains Fast Path Write related bits.

I/O Trap SMI Enable Register

The I/O Trap SMI Enable Register (F3BAR+Memory Offset

18h) allows traps for specified I/O addresses and config-

ures generation for I/O events. It also contains the enabling

bit for Fast Path Write/Read features.

If Status Fast Path Read is enabled, the CS5530A inter-

cepts and responds to reads to several status registers.

This speeds up operations, and prevents SMI generation

for reads to these registers. Status Fast Path Read is

enabled via F3BAR+Memory Offset 18h[4].

In Status Fast Path Read the CS5530A responds to reads

of the following addresses:

388h-38Bh

2x0h, 2x1h, 2x2h, 2x3h, 2x8h, and 2x9h

Note that if neither sound card nor FM I/O mapping is

enabled, then status read trapping is not possible.

If Fast Path Write is enabled, the CS5530A captures cer-

tain writes to several I/O locations. This feature prevents

two SMIs from being asserted for write operations that are

known to take two accesses (the first access is an index

and the second is data). Fast Path Write is enabled via

F3BAR+Memory Offset 18h[11].

Fast Path Write captures the data and address bit 1 (A1) of

the first access, but does not generate an SMI. A1 is stored

in F3BAR+Memory Offset 14h[15]. The second access

causes an SMI, and the data and address are captured as

in a normal trapped I/O.

In Fast Path Write, the CS5530A responds to writes to the

following addresses:

388h, 38Ah, and 38Bh

2x0h, 2x2h, and 2x8h

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