CS5530A datasheet(127/259 Pages) NSC

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Functional Description (Continued)

Table 3-68. Third Level SMI Status Reporting Registers

Bit

Description

F3BAR+Memory Offset 14h-17h

I/O Trap SMI and Fast Write Status Register (RO/RC)

Reset Value = 00000000h

31:24

Fast Path Write Even Access Data (Read Only): These bits contain the data from the last Fast Path Write Even access.

These bits change only on a fast write to an even address.

23:16

Fast Path Write Odd Access Data (Read Only): These bits contain the data from the last Fast Path Write Odd access.

These bits change on a fast write to an odd address, and also on any non-fast write.

Fast Write A1 (Read Only): This bit contains the A1 value for the last Fast Write access.

Read or Write I/O Access (Read Only): Last trapped I/O access was a read or a write? 0 = Read; 1 = Write.

Sound Card or FM Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the sound card or FM

I/O Trap? 0 = No; 1 = Yes. (Note)

Fast Path Write must be enabled, F3BAR+Memory Offset 18h[11] = 1, for the SMI to be reported here. If Fast Path Write is

disabled, the SMI is reported in bit 10 of this register.

This is the third level of SMI status reporting.

The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0].

The top level is reported at F1BAR+Memory Offset 00h/02h[1].

SMI generation enabling is at F3BAR+Memory Offset 18h[2].

DMA Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the DMA I/O Trap?

0 = No;1 =Yes.(Note)

This is the third level of SMI status reporting.

The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0].

The top level is reported at F1BAR+Memory Offset 00h/02h[1].

SMI generation enabling is at F3BAR+Memory Offset 18h[8:7].

MPU Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the MPU I/O Trap?

0 = No;1 =Yes.(Note)

This is the third level of SMI status reporting.

The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0].

The top level is reported at F1BAR+Memory Offset 00h/02h[1].

SMI generation enabling is at F3BAR+Memory Offset 18h[6:5].

Sound Card or FM Trap SMI Status (Read to Clear): SMI was caused by a trapped I/O access to the sound card or FM

I/O Trap? 0 = No; 1 = Yes. (Note)

Fast Path Write must be disabled, F3BAR+Memory Offset 18h[11] = 0, for the SMI to be reported here. If Fast Path Write is

enabled, the SMI is reported in bit 13 of this register.

This is the third level of SMI status reporting.

The second level of SMI status is reported at F3BAR+Memory Offset 10h/12h[0].

The top level is reported at F1BAR+Memory Offset 00h/02h[1].

SMI generation enabling is at F3BAR+Memory Offset 18h[2].

9:0

X-Bus Address (Read Only): Bits [9:0] contain the captured ten bits of X-Bus address.

Note: For the four SMI status bits (bits [13:10]), if the activity was a fast write to an even address, no SMI is generated regardless of the

DMA, MPU, or sound card status. If the activity was a fast write to an odd address, an SMI is generated but bit 13 is set to a 1.

CS5530A Datasheet(PDF) 127 Page - National Semiconductor (TI)

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