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Revision 1.1

Functional Description (Continued)

3.9

UNIVERSAL SERIAL BUS SUPPORT

The CS5530A integrates a Universal Serial Bus (USB) con-

troller which supports two ports. The USB controller is

OpenHCI compliant, a standard developed by Compaq,

Microsoft, and National Semiconductor. The USB core con-

sists of three main interface blocks: the USB PCI interface

controller, the USB host controller, and the USB interface

controller. Legacy keyboard and mouse controllers are also

supported for DOS compatibility with those USB devices.

This document must be used along with the following public

domain reference documents for a complete functional

description of the USB controller:

• USB Specification Revision 1.0

• OpenHCI Specification, Revision 1.0

• PCI Specification, Version 2.1

3.9.1

USB PCI Controller

The PCI controller interfaces the host controller to the PCI

bus. As a master, the PCI controller is responsible for run-

ning cycles on the PCI bus on behalf of the host controller.

As a target, the PCI controller monitors the cycles on the

PCI bus and determines when to respond to these cycles.

The USB core is a PCI target when it decodes cycles to its

internal PCI configuration registers or to its internal PCI

memory mapped I/O registers.

The USB core is implemented as a unique PCI device in

the CS5530A. It has its own PCI Header and Configuration

space. It is a single-function device, containing only Func-

tion #0. Depending on the state of the HOLD_REQ# strap

pin at reset, its PCI Device Number for Configuration

accesses varies:

If HOLD_REQ# is low, it uses pin AD29 as its IDSEL

input, appearing as Device #13h in a Geode system.

If HOLD_REQ# is high, it uses pin AD27 as its IDSEL

input, appearing as Device #11h in a Geode system.

The USB core is also affected by some bits in registers

belonging to the other (Chipset) device of the CS5530A. In

particular, the USB device can be disabled through the

Chipset device, F0 Index 43h[0], and its IDSEL can be

remapped by changing F0 Index 44h[6] (though this also

affects the Chipset device's IDSEL and is not recom-

mended).

All registers can be accessed via 8-, 16-, or 32-bit cycles

(i.e., each byte is individually selected by the byte enables).

Registers marked as Reserved, and reserved bits within a

These registers are summarized in Table 3-77. For com-

plete bit information, see Table 4-25 "USB Index xxh: USB

PCI Configuration Registers" on page 210.

Table 3-77. USB PCI Configuration Registers

USB

Index

Type

Name

00h-01h

Vendor Identification

02h-03h

Device Identification

04h-05h

R/W

Command Register

06h-07h

R/W

Status Register

08h

Device Revision ID

09h-0Bh

Class Code

0Ch

R/W

Cache Line Size

0Dh

R/W

Latency Timer

0Eh

Header Type

0Fh

BIST Register

10h-13h

R/W

Base Address Register (USB

BAR): Sets the base address of

the memory mapped USB con-

troller registers.

14h-3Bh

Reserved

3Ch

R/W

Interrupt Line Register

3Dh

Interrupt Pin Register

3Eh

Min. Grant Register

3Fh

Max. Latency Register

40h-43h

R/W

ASIC Test Mode Enable Regis-

ter

44h-45h

R/W

ASIC Operational Mode Enable

46h-47h

Reserved

48h-FFh

Reserved

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