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CS5530A Datasheet(PDF) 145 Page - National Semiconductor (TI) |
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CS5530A Datasheet(HTML) 145 Page - National Semiconductor (TI) |
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145 / 259 page  Revision 1.1 145 www.national.com Register Descriptions (Continued) Table 4-5. Function 2: PCI Header Registers for IDE Controller Summary F2 Index Width (Bits) Type Name Reset Value Reference (Table 4-18) 00h-01h 16 RO Vendor Identification Register 1078h Page 188 02h-03h 16 RO Device Identification Register 0102h Page 188 04h-05h 16 R/W PCI Command Register 0000h Page 188 06h-07h 16 RO PCI Status Register 0280h Page 188 08h 8 RO Device Revision ID Register 00h Page 188 09h-0Bh 24 RO PCI Class Code Register 010180h Page 188 0Ch 8 RO PCI Cache Line Size Register 00h Page 188 0Dh 8 RO PCI Latency Timer Register 00h Page 188 0Eh 8 RO PCI Header Type Register 00h Page 188 0Fh 8 RO PCI BIST Register 00h Page 188 10h-1Fh -- -- Reserved 00h Page 188 20h-23h 32 R/W Base Address Register (F2BAR): Sets base address for I/O mapped IDE controller configuration registers (summarized in Table 4-6). 00000001h Page 188 24h-3Fh -- -- Reserved 00h Page 188 40h-FFh -- -- Reserved xxh Page 188 Table 4-6. F2BAR: IDE Controller Configuration Registers Summary F2BAR+ I/O Offset Width (Bits) Type Name Reset Value Reference (Table 4-19) 00h 8 R/W IDE Bus Master 0 Command Register: Primary 00h Page 189 01h -- -- Reserved xxh Page 189 02h 8 R/W IDE Bus Master 0 Status Register: Primary 00h Page 189 03h -- -- Reserved xxh Page 189 04h-07h 32 R/W IDE Bus Master 0 PRD Table Address: Primary 00000000h Page 189 08h 8 R/W IDE Bus Master 1 Command Register: Secondary 00h Page 189 09h -- -- Reserved xxh Page 189 0Ah 8 R/W IDE Bus Master 1 Status Register: Secondary 00h Page 189 0Bh -- -- Reserved xxh Page 190 0Ch-0Fh 32 R/W IDE Bus Master 1 PRD Table Address: Secondary 00000000h Page 190 10h-1Fh -- -- Reserved xxh Page 190 20h-23h 32 R/W Channel 0 Drive 0: PIO Register 0000E132h Page 190 24h-27h 32 R/W Channel 0 Drive 0: DMA Control Register 00077771h Page 191 28h-2Bh 32 R/W Channel 0 Drive 1: PIO Register 0000E132h Page 191 2Ch-2Fh 32 R/W Channel 0 Drive 1: DMA Control Register 00077771h Page 191 30h-33h 32 R/W Channel 1 Drive 0: PIO Register 0000E132h Page 191 34h-37h 32 R/W Channel 1 Drive 0: DMA Control Register 00077771h Page 191 38h-3Bh 32 R/W Channel 1 Drive 1: PIO Register 0000E132h Page 191 3Ch-3Fh 32 R/W Channel 1 Drive 1: DMA Control Register 00077771h Page 191 40h-FFh -- -- Reserved xxh Page 191 |
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