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LTC2972 Datasheet(PDF) 33 Page - Linear Technology

Part # LTC2972
Description  2-Channel PMBus Power System Manager Featuring Programmable Power Good Outputs
PDF  112 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2972 Datasheet(HTML) 33 Page - Linear Technology

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For more information www.linear.com/LTC2972
MFR_PAGE_FF_MASK
The MFR_PAGE_FF_MASK command is used to select which channels respond when the global page command (PAGE
= 0xFF) is in use.
MFR_PAGE_FF_MASK Data Contents
BIT(S) SYMBOL
OPERATION
b[7:2] Reserved
Always returns 0000b
b[1] Mfr_page_ff_mask_chan1
Channel 1 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
b[0] Mfr_page_ff_mask_chan0
Channel 0 masking of global page command (PAGE = 0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
MFR_I2C_BASE_ADDRESS
The MFR_I2C_BASE_ADDRESS command determines the base value for the I2C/SMBus address byte. Offsets of 0 to
8 are added to this base address to generate the device I2C/SMBus address. The part responds to the device address.
For example, with the factory default MFR_I2C_BASE_ADDRESS of 0x5C, with both ASEL1 and ASEL0 High (Offset
N = 8), the device address would be 0x5C + 8 = 0x64.
MFR_I2C_BASE_ADDRESS Data Contents
BIT(S) SYMBOL
OPERATION
b[7] Reserved
Read only, always returns 0.
b[6:0] I2C_base_address
This 7-bit value determines the base value of the 7-bit I2C/SMBus address. See Device Address in the Operation section.
MFR_COMMAND_PLUS
MFR_DATA_PLUS0 and MFR_DATA_PLUS1
MFR_STATUS_PLUS0, and MFR_STATUS_PLUS1
Similar to the PAGE register, these registers allow the user to indirectly address memory. These registers are useful to
advanced users for reading or writing memory as described below.
Command Plus operations use a sequence of word commands to support the following:
• An alternate method for reading block data using sequential standard word reads.
• A peek operation that allows up to two additional hosts to read an internal register using PMBus word protocol
where each host has a unique page.
• A poke operation that allows up to two additional hosts to write an internal register using PMBus word protocol
where each host has a unique page.
• Peek, Poke and Command Plus block reads do not interfere with normal PMBus accesses or page values set by
PAGE. This enables multi master support for up to 3 hosts.
PMBus COMMAND DESCRIPTION



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