LPC47M192 datasheet(98/228 Pages) SMSC

98 / 228 page

SMSC DS – LPC47M192

Page 98

Rev. 03/30/05

DATASHEET

Note: A threshold of 16 is equivalent to a threshold of 15. These two cases are treated the same.

Programmed I/O - Transfers from the FIFO to the Host

In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the

FIFO. If at this time the FIFO is full it can be emptied completely in a single burst, otherwise readIntrThreshold bytes

may be read from the FIFO in a single burst.

readIntrThreshold =(16-<threshold>) data bytes in FIFO

An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16-

<threshold>). (If the threshold = 12, then the interrupt is set whenever there are 4-16 bytes in the FIFO). The host

must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred

out of the FIFO. If at this time the FIFO is full, it can be completely emptied in a single burst, otherwise a minimum of

(16-<threshold>) bytes may be read from the FIFO in a single burst.

Programmed I/O - Transfers from the Host to the FIFO

In the forward direction an interrupt occurs when serviceIntr is 0 and there are writeIntrThreshold or more bytes free

in the FIFO. At this time if the FIFO is empty it can be filled with a single burst before the empty bit needs to be

re-read. Otherwise it may be filled with writeIntrThreshold bytes.

writeIntrThreshold

(16-<threshold>) free bytes in FIFO

An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is less than or equal to

<threshold>. (If the threshold = 12, then the interrupt is set whenever there are 12 or less bytes of data in the FIFO.)

The host must respond to the request by writing data to the FIFO. If at this time the FIFO is empty, it can be

completely filled in a single burst, otherwise a minimum of (16-<threshold>) bytes may be written to the FIFO in a

single burst. This process is repeated until the last byte is transferred into the FIFO.

7.9

POWER MANAGEMENT

Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the

parallel port. For each logical device, two types of power management are provided: direct powerdown and auto

powerdown.

FDC Power Management

Direct power management is controlled by CR22. Refer to CR22 for more information.

Auto Power Management is enabled by CR23-B0. When set, this bit allows FDC to enter powerdown when all of the

following conditions have been met:

The motor enable pins of register 3F2H are inactive (zero).

The part must be idle; MSR=80H and INT = 0 (INT may be high even if MSR = 80H due to polling interrupts).

The head unload timer must have expired.

The Auto powerdown timer (10msec) must have timed out.

An internal timer is initiated as soon as the auto powerdown command is enabled. The part is then powered down

when all the conditions are met.

Disabling the auto powerdown mode cancels the timer and holds the FDC block out of auto powerdown.

Note: At least 8us delay should be added when exiting FDC Auto Powerdown mode. If the operating

environment is such that this delay cannot be guaranteed, the auto powerdown mode should not be used

and Direct powerdown mode should be used instead. The Direct powerdown mode requires at least 8us

delay at 250K bits/sec configuration and 4us delay at 500K bits/sec. The delay should be added so that the

internal microcontroller can prepare itself to accept commands.

DSR From Powerdown

If DSR powerdown is used when the part is in auto powerdown, the DSR powerdown will override the auto

powerdown. However, when the part is awakened from DSR powerdown, the auto powerdown will once again

become effective.

LPC47M192 Datasheet(PDF) 98 Page - SMSC Corporation

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