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LPC47M192 Datasheet(PDF) 22 Page - SMSC Corporation |
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LPC47M192 Datasheet(HTML) 22 Page - SMSC Corporation |
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22 / 228 page ![]() SMSC DS – LPC47M192 Page 22 Rev. 03/30/05 DATASHEET 5 BLOCK DIAGRAM LPC47M192 (128 QFP) DIGITAL DATA SEPARATOR WITH WRITE PRECOM- PENSATION SMC PROPRIETARY 82077 COMPATIBLE VERTICAL FLOPPYDISK CONTROLLER CORE WDATA WCLOCK RCLOCK RDATA Game Port Fan Control 2nd Infrared Port Multi-Mode Parallel Port with ChiProtectTM/ FDC MUX (see LPC47B27x) PD[7,0] Busy, Slct, PE, ERROR, ACK STROBE, INIT, SLCTIN, ALF LEDs Internal Bus (Data, Address, and Control lines) High-Speed 16550A UART PORT 1 TXD1, RXD1 DSR1, DTR1 DCD1, RI1 CTS1, RTS1 MPU-401 Serial Port MIDI_OUT* MIDI_IN* Keyboard/Mouse 8042 controller KCLK, MCLK KDATA, MDATA GateA20* KRESET* P12*, P16*, P17* High-Speed 16550A UART PORT 2 TXD2 (IRTX)*, RXD2 (IRRX)* DSR2*, DTR2* DCD2*, RI2* CTS2*, RTS2 * Power Mgmt IO_PME* IO_SMI* General Purpose I/O GP1[0:7]* GP2[0:2,4:7]* GP3[0:7]*, GP4[0:3]* GP5[0:7]*, GP6[0:1]* Note 1: This diagram does not show power and ground connections. Note 2: Functions with "*" are located on multifunctional pins. This diagram is designed to show the various functions available on the chip (not pin layout). Hardware Monitoring SMBus CLOCK GEN CLK32 CLOCKI LAD[3:0] LFrame LDRQ PCI_RESET LPCPD SER_IRQ PCI_CLK LPC Bus Interface SERIAL IRQ A0/RESET#/THERM#/ XNOR_OUT Vccp_IN +3.3V_IN +2.5V_IN SDA SCL VID0 VID1 VID2 VID3 12V_IN/VID4 +5V_IN HVSS HVCC +1.8V_IN +1.5V_IN FIGURE 1 – LPC47M192 BLOCK DIAGRAM |
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