LPC47M192 datasheet(68/228 Pages) SMSC

68 / 228 page

SMSC DS – LPC47M192

Page 68

Rev. 03/30/05

DATASHEET

FIFO

MODE

ONLY

INTERRUPT

IDENTIFICATION

INTERRUPT SET AND RESET FUNCTIONS

BIT 3

BIT 2 BIT 1 BIT 0

PRIORIT

Y LEVEL

INTERRUPT

TYPE

INTERRUPT

SOURCE

INTERRUPT

RESET

CONTROL

Third

Transmitter

Holding

Empty

Transmitter

Holding Register

Empty

Reading the IIR

Source of

Interrupt) or

Writing the

Transmitter

Holding Register

Fourth

MODEM

Status

Clear to Send or

Data Set Ready

or Ring Indicator

or Data Carrier

Detect

Reading the

MODEM Status

LINE CONTROL REGISTER (LCR)

Address Offset = 3H, DLAB = 0, READ/WRITE

Start LSB Data 5-8 bits MSB Parity

Stop

Serial Data

This register contains the format information of the serial line. The bit definitions are:

Bits 0 and 1

These two bits specify the number of bits in each transmitted or received serial character. The encoding of bits 0 and

1 is as follows:

The Start, Stop and Parity bits are not included in the word length.

BIT 1

BIT 0

WORD LENGTH

5 Bits

6 Bits

7 Bits

8 Bits

Bit 2

This bit specifies the number of stop bits in each transmitted or received serial character. The following table

summarizes the information.

BIT 2

WORD LENGTH

NUMBER OF

STOP BITS

5 bits

1.5

6 bits

7 bits

8 bits

Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting.

Bit 3

Parity Enable bit. When bit 3 is a logic “1”, a parity bit is generated (transmit data) or checked (receive data) between

the last data word bit and the first stop bit of the serial data. (The parity bit is used to generate an even or odd number

of 1s when the data word bits and the parity bit are summed).

LPC47M192 Datasheet(PDF) 68 Page - SMSC Corporation

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