LPC47M192 datasheet(29/228 Pages) SMSC

29 / 228 page

SMSC DS – LPC47M192

Page 29

Rev. 03/30/05

DATASHEET

7.3.5 I/O READ AND WRITE CYCLES

The LPC47M192 is the target for I/O cycles. I/O cycles are initiated by the host for register or FIFO accesses,

and will generally have minimal Sync times. The minimum number of wait-states between bytes is 1. EPP

cycles will depend on the speed of the external device, and may have much longer Sync times.

Data transfers are assumed to be exactly 1-byte. If the CPU requested a 16 or 32-bit transfer, the host will

break it up into 8-bit transfers.

See the “Low Pin Count (LPC) Interface Specification” Reference, Section 5.2, for the sequence of cycles for

the I/O Read and Write cycles.

7.3.6 DMA READ AND WRITE CYCLES

DMA read cycles involve the transfer of data from the host (main memory) to the LPC47M192. DMA write

cycles involve the transfer of data from the LPC47M192 to the host (main memory). Data will be coming from

or going to a FIFO and will have minimal Sync times. Data transfers to/from the LPC47M192 are 1, 2 or 4

bytes.

See the “Low Pin Count (LPC) Interface Specification” Reference, Section 6.4, for the field definitions and the

sequence of the DMA Read and Write cycles.

7.3.7 DMA PROTOCOL

DMA on the LPC bus is handled through the use of the LDRQ# lines from the LPC47M192 and special

encodings on LAD[3:0] from the host.

The DMA mechanism for the LPC bus is described in the “Low Pin Count (LPC) Interface Specification,”

Revision 1.0.

7.3.8 POWER MANAGEMENT

7.3.8.1

CLOCKRUN Protocol

The CLKRUN# pin is not implemented in the LPC47M192.

See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 8.1.

7.3.8.2

LPCPD Protocol

See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 8.2.

7.3.9 SYNC PROTOCOL

See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 4.2.1.8 for a table of valid SYNC

values.

7.3.9.1

Typical Usage

The SYNC pattern is used to add wait states. For read cycles, the LPC47M192 immediately drives the

SYNC pattern upon recognizing the cycle. The host immediately drives the sync pattern for write cycles. If

the LPC47M192 needs to assert wait states, it does so by driving 0101 or 0110 on LAD[3:0] until it is

ready, at which point it will drive 0000 or 1001. The LPC47M192 will choose to assert 0101 or 0110, but

not switch between the two patterns.

The data (or wait state SYNC) will immediately follow the 0000 or 1001 value. The SYNC value of 0101 is

intended to be used for normal wait states, wherein the cycle will complete within a few clocks. The

LPC47M192 uses a SYNC of 0101 for all wait states in a DMA transfer.

The SYNC value of 0110 is intended to be used where the number of wait states is large. This is provided

for EPP cycles, where the number of wait states could be quite large (>1 microsecond). However, the

LPC47M192 uses a SYNC of 0110 for all wait states in an I/O transfer.

The SYNC value is driven within 3 clocks.

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