LPC47M192 datasheet(89/228 Pages) SMSC

89 / 228 page

SMSC DS – LPC47M192

Page 89

Rev. 03/30/05

DATASHEET

Vocabulary

The following terms are used in this document:

assert: When a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state.

forward: Host to Peripheral communication.

reverse: Peripheral to Host communication

Pword:

A port word; equal in size to the width of the LPC interface. For this implementation, PWord is always 8 bits.

A high level.

A low level.

These terms may be considered synonymous:

PeriphClk, nAck

HostAck, nAutoFd

PeriphAck, Busy

nPeriphRequest, nFault

nReverseRequest, nInit

nAckReverse, PError

Xflag, Select

ECPMode, nSelectln

HostClk, nStrobe

Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14,

1993. This document is available from Microsoft.

The bit map of the Extended Parallel Port registers is:

Note

data

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

ecpAFifo

Addr/RLE

Address or RLE field

dsr

nBusy

nAck

PError

Select

nFault

dcr

Direction

ackIntEn

SelectIn

nInit

autofd

strobe

cFifo

Parallel Port Data FIFO

ecpDFifo

ECP Data FIFO

tFifo

Test FIFO

cnfgA

cnfgB

compress

intrValue

Parallel Port IRQ

Parallel Port DMA

ecr

MODE

nErrIntrEn

dmaEn

serviceIntr

full

empty

Note 1: These registers are available in all modes.

Note 2: All FIFOs use one common 16 byte FIFO.

Note 3: The ECP Parallel Port Config Reg B reflects the IRQ and DMA channel selected by the Configuration

Registers.

ECP IMPLEMENTATION STANDARD

This specification describes the standard interface to the Extended Capabilities Port (ECP). All LPC devices

supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft.

For a description of the ECP Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA

Interface Standard, Rev. 1.14, July 14, 1993. This document is available from Microsoft.

Description

The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT

port if ECP is not required. The port is designed to be simple and requires a small number of gates to implement. It

does not do any “protocol” negotiation, rather it provides an automatic high burst-bandwidth channel that supports

DMA for ECP in both the forward and reverse directions.

Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum

bandwidth requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the

standard parallel port to improve compatibility mode transfer speed.

The port also supports run length encoded (RLE) decompression (required) in hardware. Compression is

accomplished by counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is

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