LPC47M192 datasheet(84/228 Pages) SMSC

84 / 228 page

SMSC DS – LPC47M192

Page 84

Rev. 03/30/05

DATASHEET

HOST

CONNECTOR

PIN NUMBER

STANDARD

EPP

ECP

(User Defined)

PError,

nAckReverse (3)

SLCT

(User Defined)

Select

nALF

nDatastb

nAutoFd,

HostAck(3)

nERROR

(User Defined)

nFault (1)

nPeriphRequest (3)

nINIT

nRESET

nInit(1)

nReverseRqst(3)

nSLCTIN

nAddrstrb

nSelectIn(1,3)

(1) = Compatible Mode

(3) = High Speed Mode

Note:

For the cable interconnection required for ECP support and the Slave Connector pin numbers, refer to the

IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. This document is

available from Microsoft.

7.8.1 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES

DATA PORT

ADDRESS OFFSET = 00H

The Data Port is located at an offset of ‘00H’ from the base address. The data register is cleared at initialization by

RESET. During a WRITE operation, the Data Register latches the contents of the internal data bus. The contents of

this register are buffered (non inverting) and output onto the PD0 - PD7 ports. During a READ operation in SPP

mode, PD0 - PD7 ports are buffered (not latched) and output to the host CPU.

STATUS PORT

ADDRESS OFFSET = 01H

The Status Port is located at an offset of ‘01H’ from the base address. The contents of this register are latched for

the duration of a read cycle. The bits of the Status Port are defined as follows:

BIT 0 TMOUT - TIME OUT

This bit is valid in EPP mode only and indicates that a 10 usec time out has occurred on the EPP bus. A logic O

means that no time out error has occurred; a logic 1 means that a time out error has been detected. This bit is

cleared by a RESET. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device

3 Configuration Registers) is ‘0’, writing a one to this bit clears the TMOUT status bit. Writing a zero to this bit has no

effect. If the TIMEOUT_SELECT bit (bit 4 of the Parallel Port Mode Register 2, 0xF1 in Logical Device 3

Configuration Registers) is ‘1’, the TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register.

BITS 1, 2 - are not implemented as register bits, during a read of the Printer Status Register these bits are a low

level.

BIT 3 nERR – nERROR

The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic 0 means an error

has been detected; a logic 1 means no error has been detected.

BIT 4 SLT - PRINTER SELECTED STATUS

The level on the SLCT input is read by the CPU as bit 4 of the Printer Status Register. A logic 1 means the printer is

on line; a logic 0 means it is not selected.

BIT 5 PE - PAPER END

The level on the PE input is read by the CPU as bit 5 of the Printer Status Register. A logic 1 indicates a paper end;

a logic 0 indicates the presence of paper.

LPC47M192 Datasheet(PDF) 84 Page - SMSC Corporation

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