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LPC47M192 Datasheet(PDF) 83 Page - SMSC Corporation |
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LPC47M192 Datasheet(HTML) 83 Page - SMSC Corporation |
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83 / 228 page  SMSC DS – LPC47M192 Page 83 Rev. 03/30/05 DATASHEET 7.7.7.1 Activate and I/O Base address When the Activate bit D0 is ‘0’, the MPU-401 I/O base address decoder is disabled, the IRQ is always deasserted, and the MPU-401 hardware is in a minimum power-consumption state. When the Activate bit is ‘1’, the MPU-401 I/O base address decoder and the IRQ are enabled, and the MPU-401 hardware is fully powered. Register 0x60 is the MPU-401 I/O Base Address High Byte, register 0x61 is the MPU-401 I/O Base Address Low Byte. The MPU-401 I/O base address is programmable on even-byte boundaries. The valid MPU-401 I/O base address range is 0x0100 – 0x0FFE. See Section “Host Interface”. 7.8 PARALLEL PORT The LPC47M192 incorporates an IBM XT/AT compatible parallel port. This supports the optional PS/2 type bi- directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the Configuration Registers for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. The parallel port also incorporates SMSC’s ChiProtect circuitry, which prevents possible damage to the parallel port due to printer power-up. The functionality of the Parallel Port is achieved through the use of eight addressable ports, with their associated registers and control gating. The control and data port are read/write by the CPU, the status port is read/write in the EPP mode. The address map of the Parallel Port is shown below: DATA PORT BASE ADDRESS + 00H STATUS PORT BASE ADDRESS + 01H CONTROL PORT BASE ADDRESS + 02H EPP ADDR PORT BASE ADDRESS + 03H EPP DATA PORT 0 BASE ADDRESS + 04H EPP DATA PORT 1 BASE ADDRESS + 05H EPP DATA PORT 2 BASE ADDRESS + 06H EPP DATA PORT 3 BASE ADDRESS + 07H The bit map of these registers is: D0 D1 D2 D3 D4 D5 D6 D7 Note DATA PORT PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 1 STATUS PORT TMOUT 0 0 nERR SLCT PE nACK nBUSY 1 CONTROL PORT STROBE AUTOFD nINIT SLC IRQE PCD 0 0 1 EPP ADDR PORT PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2 EPP DATA PORT 0 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2 EPP DATA PORT 1 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2 EPP DATA PORT 2 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2 EPP DATA PORT 3 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 2 Note 1: These registers are available in all modes. Note 2: These registers are only available in EPP mode. Table 39 - Parallel Port Connector HOST CONNECTOR PIN NUMBER STANDARD EPP ECP 1 83 nSTROBE nWrite nStrobe 2-9 68-75 PD<0:7> PData<0:7> PData<0:7> 10 80 nACK Intr nAck 11 79 BUSY nWait Busy, PeriphAck(3) |
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