DSP56857 datasheet(208/662 Pages) FREESCALE

208 / 662 page

5685X Digital Signal Controller User Manual, Rev. 4

8-30

Freescale Semiconductor

Figure 8-23. IRQ Pending Register 4 (IRQP4)

See Programmer’s Sheet on Appendix page B - 42

8.7.15.1 Pending IRQs (PENDING)—Bits 2–69

•

0 = IRQ pending for this vector number

•

1 = No IRQ pending for this vector number

8.7.15.2 Reserved—Bits 70–80

These bits are reserved or not implemented. They are read as 1, but they cannot be modified by

writing.

8.7.16 Interrupt Control Register (ICTL)

Figure 8-24. Interrupt Control Register (ICTL)

See Programmer’s Sheet on Appendix page B - 43

8.7.16.1 Interrupt (INT)—Bit 15

This bit reflects the state of the interrupt to the 56800E core.

•

0 = No interrupt is being sent to the core

•

1 = An interrupt is being sent to the core

8.7.16.2 Interrupt Priority Level (IPIC)—Bits 14–13

These bits reflect the state of the new interrupt priority level bits being presented to the 56800E

core at the time the last IRQ was taken. This field is only updated when the 56800E core jumps to

a new interrupt service routine.

Note:

Nested interrupts may cause this field to be updated before the original interrupt

service routine can read it.

•

00 = Required nested exception priority levels are 0, 1, 2, or 3

Base + $14

Read

PENDING[69:65]

Write

Reset

1111

11111111

1111

Base + $1A

14 13 12 11 10

Read

INT

IPIC

VAB

INT_DIS

IRQB STATE IRQA STATE

IRQB EDG

IRQA EDG

Write

Reset

00000

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