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SC16C554DB Datasheet(PDF) 37 Page - NXP Semiconductors

Part # SC16C554DB
Description  5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
PDF  51 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SC16C554DB Datasheet(HTML) 37 Page - NXP Semiconductors

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9397 750 13133
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 — 9 February 2005
37 of 51
Philips Semiconductors
SC16C554B/554DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs
[1]
Applies to external clock, crystal oscillator max 24 MHz.
[2]
Maximum frequency =
[3]
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
10.1 Timing diagrams
t28d
delay from start to reset
TXRDY
-8 TRCLK
[3]
-8 TRCLK
[3]
-8 TRCLK
[3]
ns
t30s
address setup time
10
-
10
-
10
-
ns
t30w
chip select strobe width
25 pF load
[1] 90
-
26
-
23
-
ns
t30h
address hold time
15
-
15
-
15
-
ns
t30d
read cycle delay
25 pF load
20
-
20
-
20
-
ns
t31d
delay from CS to data
25 pF load
-
90
-
26
-
23
ns
t31h
data disable time
25 pF load
-
15
-
15
-
15
ns
t32s
write strobe setup time
10
-
10
-
10
-
ns
t32h
write strobe hold time
10
-
10
-
10
-
ns
t32d
write cycle delay
25
-
25
-
20
-
ns
t33s
data setup time
20
-
15
-
15
-
ns
t33h
data hold time
15
-
5
-
5
-
ns
tRESET
RESET pulse width
200
-
40
-
40
-
ns
N
baud rate divisor
1 TRCLK
[3]
216
− 1
TRCLK [3]
1TRCLK
[3]
216
− 1
TRCLK [3]
1TRCLK
[3]
216
− 1
TRCLK [3]
ns
Table 26:
Dynamic characteristics …continued
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5.0 V ± 10 %, unless otherwise specified.
Symbol Parameter
Conditions
2.5 V
3.3 V
5.0 V
Unit
Min
Max
Min
Max
Min
Max
1
t
3w
-------
Fig 14. General read timing in 68 mode
002aaa210
t30s
A0 to A4
CS
R/W
D0 to D7
t30w
t30h
t30d
t31h
t32s
t31d



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