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SC16C554DB Datasheet(PDF) 41 Page - NXP Semiconductors |
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SC16C554DB Datasheet(HTML) 41 Page - NXP Semiconductors |
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41 / 51 page ![]() 9397 750 13133 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 01 — 9 February 2005 41 of 51 Philips Semiconductors SC16C554B/554DB 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs Fig 21. Receive ready timing in non-FIFO mode D0 D1 D2 D3 D4 D5 D6 D7 002aab063 next data start bit stop bit parity bit t25d RX RXRDY IOR active data ready start bit data bits (0 to 7) active t26d Fig 22. Receive ready timing in FIFO mode D0 D1 D2 D3 D4 D5 D6 D7 002aab064 first byte that reaches the trigger level stop bit parity bit t25d RX RXRDY IOR active data ready start bit data bits (0 to 7) active t26d |
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