SC16C554DB datasheet(27/51 Pages) PHILIPS

27 / 51 page

9397 750 13133

Product data sheet

Rev. 01 — 9 February 2005

27 of 51

Philips Semiconductors

SC16C554B/554DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

7.4 Interrupt Status Register (ISR)

The SC16C554B/554DB provides four levels of prioritized interrupts to minimize external

software interaction. The Interrupt Status Register (ISR) provides the user with four

interrupt status bits. Performing a read cycle on the ISR will provide the user with the

highest pending interrupt level to be serviced. No other interrupts are acknowledged until

the pending interrupt is serviced. Whenever the interrupt status register is read, the

interrupt status is cleared. However, it should be noted that only the current pending

interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the

interrupt status bits. Table 13 “Interrupt source” shows the data values (bits 0 to 5) for the

four prioritized interrupt levels and the interrupt sources associated with each of these

interrupt levels.

Table 12:

RCVR trigger levels

FCR[7]

FCR[6]

RX FIFO trigger level

001

014

108

1114

Table 13:

Interrupt source

Priority

level

ISR[5]

ISR[4]

ISR[3]

ISR[2]

ISR[1]

ISR[0]

Source of the interrupt

000110

LSR (Receiver Line Status

000100

RXRDY (Receive Data

Ready)

001100

RXRDY (Receive Data

time-out)

000010

TXRDY (Transmitter Holding

000000

MSR (Modem Status

Table 14:

Interrupt Status Register bits description

Bit

Symbol

Description

7:6

ISR[7:6]

FIFOs enabled. These bits are set to a logic 0 when the FIFO is not

being used. They are set to a logic 1 when the FIFOs are enabled.

Logic 0 or cleared = default condition.

5:4

ISR[5:4]

Reserved; set to ‘0’.

3:1

ISR[3:1]

INT priority bits 2 to 0. These bits indicate the source for a pending

interrupt at interrupt priority levels 1, 2, and 3 (see Table 13).

Logic 0 or cleared = default condition.

ISR[0]

INT status.

Logic 0 = An interrupt is pending and the ISR contents may be used

as a pointer to the appropriate interrupt service routine.

Logic 1 = No interrupt pending (normal default condition).

SC16C554DB Datasheet(PDF) 27 Page - NXP Semiconductors

SC16C554DB Datasheet(HTML) 27 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

Datasheet Download

Link URL