SC16C554DB datasheet(24/51 Pages) PHILIPS

24 / 51 page

9397 750 13133

Product data sheet

Rev. 01 — 9 February 2005

24 of 51

Philips Semiconductors

SC16C554B/554DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

7.1 Transmit (THR) and Receive (RHR) Holding Registers

The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and

Transmit Shift Register (TSR). The status of the THR is provided in the Line Status

THR, providing that the THR or TSR is empty. The THR empty ﬂag in the LSR register will

be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.

Note that a write operation can be performed when the THR empty ﬂag is set

(logic 0 = FIFO full; logic 1 = at least one FIFO location available).

The serial receive section also contains an 8-bit Receive Holding Register (RHR).

Receive data is removed from the SC16C554B/554DB and receive FIFO by reading the

RHR register. The receive section provides a mechanism to prevent false starts. On the

falling edge of a start or false start bit, an internal receiver counter starts counting clocks

at the 16

× clock rate. After 71⁄

2 clocks, the start bit time should be shifted to the center of

the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.

Evaluating the start bit in this manner prevents the receiver from assembling a false

character. Receiver status codes will be posted in the LSR.

7.2 Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter

empty, line status and modem status registers. These interrupts would normally be seen

on the INTA to INTD output pins in the 16 mode, or on wire-OR IRQ output pin in the

68 mode.

Table 10:

Interrupt Enable Register bits description

Bit

Symbol

Description

7:4

IER[7:4]

Reserved; set to ‘0’.

IER[3]

Modem Status Interrupt.

Logic 0 = Disable the modem status register interrupt (normal default

condition).

Logic 1 = Enable the modem status register interrupt.

IER[2]

Receive Line Status interrupt.

Logic 0 = Disable the receiver line status interrupt (normal default condition).

Logic 1 = Enable the receiver line status interrupt.

IER[1]

Transmit Holding Register interrupt. This interrupt will be issued whenever the

THR is empty, and is associated with LSR[1].

Logic 0 = Disable the transmitter empty interrupt (normal default condition).

Logic 1 = Enable the transmitter empty interrupt.

IER[0]

Receive Holding Register interrupt. This interrupt will be issued when the FIFO

has reached the programmed trigger level, or is cleared when the FIFO drops

below the trigger level in the FIFO mode of operation.

Logic 0 = Disable the receiver ready interrupt (normal default condition).

Logic 1 = Enable the receiver ready interrupt.

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