SC16C554DB datasheet(33/51 Pages) PHILIPS

33 / 51 page

9397 750 13133

Product data sheet

Rev. 01 — 9 February 2005

33 of 51

Philips Semiconductors

SC16C554B/554DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

[1]

Whenever any MSR[3:0] is set to logic 1, a Modem Status Interrupt will be generated.

7.9 Scratchpad Register (SPR)

The SC16C554B/554DB provides a temporary data register to store 8 bits of user

information.

7.10 SC16C554B/554DB external reset conditions

MSR[1]

∆DSR [1]

Logic 0 = No DSR change (normal default condition).

Logic 1 = The DSR input to the SC16C554B/554DB has changed state

since the last time it was read. A modem Status Interrupt will be

generated.

MSR[0]

∆CTS [1]

Logic 0 = No CTS change (normal default condition).

Logic 1 = The CTS input to the SC16C554B/554DB has changed state

since the last time it was read. A modem Status Interrupt will be

generated.

Table 21:

Modem Status Register bits description …continued

Bit

Symbol

Description

Table 22:

Reset state for registers

Reset state

IER

IER[7:0] = 0

ISR

ISR[7:1] = 0; ISR[0] = 1

LCR

LCR[7:0] = 0

MCR

MCR[7:0] = 0

LSR

LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0

MSR

MSR[7:4] = input signals; MSR[3:0] = 0

FCR

FCR[7:0] = 0

Table 23:

Reset state for outputs

Output

Reset state

TXA, TXB, TXC, TXD

HIGH

RTSA, RTSB, RTSC, RTSD

HIGH

DTRA, DTRB, DTRC, DTRD

HIGH

RXRDY

HIGH

TXRDYLOW

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