SC16C554DB datasheet(18/51 Pages) PHILIPS

18 / 51 page

9397 750 13133

Product data sheet

Rev. 01 — 9 February 2005

18 of 51

Philips Semiconductors

SC16C554B/554DB

5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 16-byte FIFOs

6.5 Hardware/software and time-out interrupts

Following a reset, if the transmitter interrupt is enabled, the SC16C554B/554DB will issue

an interrupt to indicate that the Transmit Holding Register is empty. This interrupt must be

serviced prior to continuing operations. The LSR register provides the current singular

highest priority interrupt only. Only after servicing the higher pending interrupt will the

lower priority interrupt(s) be reﬂected in the status register. Servicing the interrupt without

investigating further interrupt conditions can result in data errors.

When two interrupt conditions have the same priority, it is important to service these

interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt

priority (when enabled by IER[0]). The receiver issues an interrupt after the number of

characters have reached the programmed trigger level. In this case, the

SC16C554B/554DB FIFO may hold more characters than the programmed trigger level.

Following the removal of a data byte, the user should re-check LSR[0] for additional

characters. A Receive Time Out will not occur if the receive FIFO is empty. The time-out

counter is reset at the center of each stop bit received or each time the receive holding

In the 16 mode for the PLCC68 package, the system/board designer can optionally

provide software controlled 3-state interrupt operation. This is accomplished by INTSEL

and MCR[3]. When INTSEL interface pin is left open or made a logic 0, MCR[3] controls

the 3-state interrupt outputs, INTA to INTD. When INTSEL is a logic 1, MCR[3] has no

effect on the INTA to INTD outputs, and the package operates with interrupt outputs

enabled continuously.

6.6 Programmable baud rate generator

The SC16C554B/554DB supports high speed modem technologies that have increased

input data rates by employing data compression schemes. For example, a 33.6 kbit/s

modem that employs data compression may require a 115.2 kbit/s input data rate.

A 128.0 kbit/s ISDN modem that supports data compression may need an input data rate

of 460.8 kbit/s.

(1) RTS is de-asserted when the receiver receives the ﬁrst data bit of the sixteenth byte. The receive FIFO is full after ﬁnishing

the sixteenth byte.

(2) RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing, or there is

more than one byte of space available.

(3) When the receive FIFO is full, the ﬁrst receive buffer register read re-asserts RTS.

Fig 10. RTS functional timing waveforms, RCV FIFO trigger level = 14 bytes

byte 14

byte 15

RTS

IOR

(RD RBR)

Start

byte 18

Stop

Start

byte 16

Stop

002aaa051

RTS released after the

first data bit of byte 16

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