HD64F2145 datasheet(277/829 Pages) RENESAS

277 / 829 page

Rev. 2.0, 08/02, page 237 of 788

tf1

tf2

tf255

tf256

tH1

tH2

tH3

tH255

tH256

1 conversion cycle

tf1 = tf2 = tf3 = ··· = tf255 = tf256 = T 64

tH1 + tH2 + tH3 + ··· + tH255 + tH256 = TH

tf1

tf2

tf63

tf64

tH1

tH2

tH3

tH63

tH64

1 conversion cycle

tf1 = tf2 = tf3 = ··· = tf63 = tf64 = T 256

tH1 + tH2 + tH3 + ··· + tH63 + tH64 = TH

a. CFS = 0 [base cycle = resolution (T)

64]

b. CFS = 1 [base cycle = resolution (T)

256]

Figure 10.4 Output Waveform (OS = 1, DADR corresponds to T

An example of setting CFS to 1 (basic cycle = resolution (T)

× 256) and OS to 1 (PWMX inverted

output) is shown as an additional pulse. When CFS is set to 1, the duty ratio of the basic pulse is

determined by the upper eight bits (DA13 to DA6) in DADR, and the position of the additional

pulse is determined by the following six bits (DA5 to DA0) as shown in figure 10.5.

Table 10.4 shows the position of the additional pulse.

Basic pulse duty ratio

DA13 DA12 DA11 DA10 DA9

DA8

DA7

DA6

DA5

DA4

DA3

DA2

DA1

DA0

CFS

Additional pulse position

Figure 10.5 D/A Data Register Configuration when CFS = 1

Here, the case of DADR = H’0207 (B’0000 0010 0000 0111) is considered. Figure 10.6 shows an

output waveform. Because CFS = 1 and the value of upper eight bits is B’0000 0010, the duty

ratio of the basic pulse is 2/256

× (T) of high width.

Since the value of the following six bits is B’0000 01, the additional pulse is output at the position

of basic pulse No. 63 as shown in table 10.4. Only 1/256

× (T) of the additional pulse is added to

the basic pulse.

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