HD64F2145 datasheet(282/829 Pages) RENESAS

282 / 829 page

Rev. 2.0, 08/02, page 242 of 788

Figure 11.1 shows a block diagram of the FRT.

Clock selector

Clock

Compare-match A

OCRA (H/L)

Comparator A

Internal data bus

FRC (H/L)

Comparator B

OCRB (H/L)

ICRA (H/L)

ICRB (H/L)

ICRC (H/L)

ICRD (H/L)

TCSR

FTCI

FTOB

FTIA

External clock

Internal clock

ø/2

ø/8

ø/32

FTIB

FTIC

FTID

FTOA

Compare-match B

Overflow

Clear

Input capture

TIER

TCR

TOCR

ICIA

ICIB

ICIC

ICID

Interrupt signal

Legend

OCRA, OCRB

OCRAR,OCRAF

OCRDM

FRC

ICRA to D

TCSR

TIER

TCR

TOCR

: Output compare register A, B (16-bit)

: Output compare register AR, AF (16-bit)

: Output compare register DM (16-bit)

: Free-running counter (16-bit)

: Input capture registers A to D (16-bit)

: Timer control/status register (8-bit)

: Timer interrupt enable register (8-bit)

: Timer control register (8-bit)

: Timer output compare control register (8-bit)

OCIA

OCIB

FOVI

OCRAR/F (H/L)

OCRDM L

Comparator M

Compare-match M

× 1

× 2

Control logic

Figure 11.1 Block Diagram of 16-Bit Free-Running Timer

HD64F2145 Datasheet(PDF) 282 Page - Renesas Technology Corp

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