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SAF-C161PI Datasheet(PDF) 38 Page - Infineon Technologies AG |
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SAF-C161PI Datasheet(HTML) 38 Page - Infineon Technologies AG |
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38 / 400 page  &3, 0HPRU\ 2UJDQL]DWLRQ User’s Manual 3-2 1999-08 Most internal memory areas are mapped into segment 0, the system segment. The upper 4 KByte of segment 0 (00’F000 H...00’FFFFH) hold the Internal RAM and Special Function Register Areas (SFR and ESFR). The lower 32 KByte of segment 0 (00’0000 H...00’7FFFH) may be occupied by a part of the on-chip ROM/Flash/OTP memory and is called the Internal ROM area. This ROM area can be remapped to segment 1 (01’0000 H...01’7FFFH), to enable external memory access in the lower half of segment 0, or the internal ROM may be disabled at all. Code and data may be stored in any part of the internal memory areas, except for the SFR blocks, which may be used for control / data, but not for instructions. Note: Accesses to the internal ROM area on ROMless devices will produce unpredictable results. Bytes are stored at even or odd byte addresses. Words are stored in ascending memory locations with the low byte at an even byte address being followed by the high byte at the next odd byte address. Double words (code only) are stored in ascending memory locations as two subsequent words. Single bits are always stored in the specified bit position at a word address. Bit position 0 is the least significant bit of the byte at an even byte address, and bit position 15 is the most significant bit of the byte at the next odd byte address. Bit addressing is supported for a part of the Special Function Registers, a part of the internal RAM and for the General Purpose Registers. Figure 3-2 Storage of Words, Byte and Bits in a Byte Organized Memory Note: Byte units forming a single word or a double word must always be stored within the same physical (internal, external, ROM, RAM) and organizational (page, segment) memory area. |
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