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SAF-C161PI Datasheet(PDF) 45 Page - Infineon Technologies AG |
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SAF-C161PI Datasheet(HTML) 45 Page - Infineon Technologies AG |
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45 / 400 page  &3, 0HPRU\ 2UJDQL]DWLRQ User’s Manual 3-9 1999-08 3.3 The On-Chip XRAM The C161PI provides access to 2KByte of on-chip extension RAM. The XRAM is located within data page 3 (organized as 1K*16). As the XRAM is connected to the internal XBUS it is accessed like external memory, however, no external bus cycles are executed for these accesses. XRAM accesses are globally enabled or disabled via bit XPEN in register SYSCON. This bit is cleared after reset and may be set via software during the initialization to allow accesses to the on-chip XRAM. When the XRAM is disabled (default after reset) all accesses to the XRAM area are mapped to external locations. The XRAM may be used for both code (instructions) and data (variables, user stack, tables, etc.) storage. Code fetches are always made on even byte addresses. The highest possible code storage location in the XRAM is either 00’E7FE H for single word instructions, or 00’E7FC H for double word instructions. The respective location must contain a branch instruction (unconditional), because sequential boundary crossing from XRAM to external memory is not supported and causes erroneous results. Any word and byte data read accesses may use the indirect or long 16-bit addressing modes. There is no short addressing mode for XRAM operands. Any word data access is made to an even byte address. The highest possible word data storage location in the XRAM is 00’E7FE H. For PEC data transfers the XRAM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers. Note: As the XRAM appears like external memory it cannot be used for the C161PI’s system stack or register banks. The XRAM is not provided for single bit storage and therefore is not bit addressable. The on-chip XRAM is accessed with the following bus cycles: • Normal ALE • No cycle time waitstates (no READY control) • No tristate time waitstate • No Read/Write delay • 16-bit demultiplexed bus cycles (4 TCL). Even if the XRAM is used like external memory it does not occupy BUSCONx/ ADDRSELx registers but rather is selected via additional dedicated XBCON/XADRS registers. These registers are mask-programmed and are not user accessible. With these registers the address area 00’E000 H to 00’E7FFH is reserved for XRAM accesses. |
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