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SAF-C161PI Datasheet(PDF) 72 Page - Infineon Technologies AG

Part # SAF-C161PI
Description  16-Bit Single-Chip Microcontroller
PDF  400 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

SAF-C161PI Datasheet(HTML) 72 Page - Infineon Technologies AG

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User’s Manual
4-24
1999-08
The DPP registers are implicitly used, whenever data accesses to any memory location
are made via indirect or direct long 16-bit addressing modes (except for override
accesses via EXTended instructions and PEC data transfers). After reset, the Data Page
Pointers are initialized in a way that all indirect or direct long 16-bit addresses result in
identical 18-bit addresses. This allows to access data pages 3...0 within segment 0 as
shown in the figure below. If the user does not want to use any data paging, no further
action is required.
Data paging is performed by concatenating the lower 14 bits of an indirect or direct long
16-bit address with the contents of the DPP register selected by the upper two bits of the
16-bit address. The contents of the selected DPP register specify one of the 1024
possible data pages. This data page base address together with the 14-bit page offset
forms the physical 24-bit address (selectable part is driven to the address pins).
In case of non-segmented memory mode, only the two least significant bits of the
implicitly selected DPP register are used to generate the physical address. Thus,
extreme care should be taken when changing the content of a DPP register, if a non-
segmented memory model is selected, because otherwise unexpected results could
occur.
In case of the segmented memory mode the selected number of segment address bits
(via bitfield SALSEL) of the respective DPP register is output on the respective segment
address pins of Port 4 for all external data accesses.
A DPP register can be updated via any instruction, which is capable of modifying an SFR.
Note: Due to the internal instruction pipeline, a new DPP value is not yet usable for the
operand address calculation of the instruction immediately following the
instruction updating the DPP register.
Figure 4-6
Addressing via the Data Page Pointers
After reset or with segmentation disabled the DPP registers select data pages 3...0.
All of the internal memory is accessible in these cases.



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