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SAF-C161PI Datasheet(PDF) 23 Page - Infineon Technologies AG |
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SAF-C161PI Datasheet(HTML) 23 Page - Infineon Technologies AG |
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23 / 400 page  &3, $UFKLWHFWXUDO2YHUYLHZ User’s Manual 2-7 1999-08 2.1.2 Programmable Multiple Priority Interrupt System The following enhancements have been included to allow processing of a large number of interrupt sources: 1. Peripheral Event Controller (PEC): This processor is used to off-load many interrupt requests from the CPU. It avoids the overhead of entering and exiting interrupt or trap routines by performing single-cycle interrupt-driven byte or word data transfers between any two locations in segment 0 with an optional increment of either the PEC source or the destination pointer. Just one cycle is ’stolen’ from the current CPU activity to perform a PEC service. 2. Multiple Priority Interrupt Controller: This controller allows all interrupts to be placed at any specified priority. Interrupts may also be grouped, which provides the user with the ability to prevent similar priority tasks from interrupting each other. For each of the possible interrupt sources there is a separate control register, which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher prioritized service request. For standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. 3. 3)Multiple Register Banks: This feature allows the user to specify up to sixteen general purpose registers located anywhere in the internal RAM. A single one-machine-cycle instruction allows to switch register banks from one task to another. 4. 4)Interruptable Multiple Cycle Instructions: Reduced interrupt latency is provided by allowing multiple-cycle instructions (multiply, divide) to be interruptable. With an interrupt response time within a range from just 5 to 10 CPU clock cycles (in case of internal program execution), the C161PI is capable of reacting very fast on non- deterministic events. Its fast external interrupt inputs are sampled every CPU clock cycle and allow to recognize even very short external signals. The C161PI also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so called ’Hardware Traps’. Hardware traps cause an immediate non-maskable system reaction which is similiar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except for another higher prioritized trap service being in progress, a hardware trap will interrupt any current program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. Software interrupts are supported by means of the ’TRAP’ instruction in combination with an individual trap (interrupt) number. |
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