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SAF-C161PI Datasheet(PDF) 61 Page - Infineon Technologies AG |
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SAF-C161PI Datasheet(HTML) 61 Page - Infineon Technologies AG |
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61 / 400 page  &3, 7KH &HQWUDO 3URFHVVLQJ 8QLW &38 User’s Manual 4-13 1999-08 The operand and instruction accesses listed below can extend the execution time of an instruction: • Internal code memory operand reads (same for byte and word operand reads) • Internal RAM operand reads via indirect addressing modes • Internal SFR operand reads immediately after writing • External operand reads • External operand writes • Jumps to non-aligned double word instructions in the internal ROM space • Testing Branch Conditions immediately after PSW writes 4.5 CPU Special Function Registers The core CPU requires a set of Special Function Registers (SFRs) to maintain the system state information, to supply the ALU with register-addressable constants and to control system and bus configuration, multiply and divide ALU operations, code memory segmentation, data memory paging, and accesses to the General Purpose Registers and the System Stack. The access mechanism for these SFRs in the CPU core is identical to the access mechanism for any other SFR. Since all SFRs can simply be controlled by means of any instruction, which is capable of addressing the SFR memory space, a lot of flexibility has been gained, without the need to create a set of system-specific instructions. Note, however, that there are user access restrictions for some of the CPU core SFRs to ensure proper processor operations. The instruction pointer IP and code segment pointer CSP cannot be accessed directly at all. They can only be changed indirectly via branch instructions. The PSW, SP, and MDC registers can be modified not only explicitly by the programmer, but also implicitly by the CPU during normal instruction processing. Note that any explicit write request (via software) to an SFR supersedes a simultaneous modification by hardware of the same register. Note: Any write operation to a single byte of an SFR clears the non-addressed complementary byte within the specified SFR. Non-implemented (reserved) SFR bits cannot be modified, and will always supply a read value of ’0’. |
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